Understanding the mechanisms involved in designing high-speed analog-to-digital converter (ADC) front ends is sometimes like an art of its own. Simply placing a balun down and drawing two trace lines from the balun’s secondary outputs to the ADC’s inputs is not recommended for any high-speed analog receiver front end design. Baluns are notorious for being parasitic-sensitive on bandwidth, along with other nuisances. In this article, we’ll show you how to get the most out of your passive analog-input design using a balun. The added benefit is that you don’t need a costly balun nor a costly attenuation pad in order to achieve the bandwidth you want.

Let’s begin with the assumption that you don’t need to DC-couple; that is, sample the DC frequency bin. Because a balun does not require an additional power supply, the advantages of using one include lower overall power consumption and smaller board space requirements. Additionally, with no extra power supply to contend with, a balun won’t add noise to the overall radio-frequency (RF) signal chain that leads up to the ADC itself, which means that no degradation in the signal-to-noise ratio (SNR) or noise spectral density will occur.

Figure 1 shows two different baluns used in the same application with TI’s 16-bit, dual-channel ADC3669 ADC. Even though both baluns are rated for the same bandwidth, they will ultimately respond differently given the combination of the ADC’s varying input impedance from the ADC’s internal sample network, as well as the printed circuit board (PCB) trace parasitics itself. Notice that with no “match” applied with either balun, the bandwidth falls quite rapidly [1].

Take a close look at the balun’s PCB footprint and layout recommendation in the data sheet. We recommend following these recommendations exactly, or else the balun will respond differently. The balun was characterized using this footprint both for data-sheet collection and measuring its S-parameters, and will only perform up to specifications under these circumstances.

To understand the balun’s phase imbalance over your specific bandwidth, note that the poorer the balun’s inherent phase imbalance, the worse even-order distortion (second harmonic distortion [HD2]) the ADC will manifest. If HD2 is important to your frequency planning application, we recommend picking a balun with good phase imbalance. There is really no good guidance on this, as each ADC can also have its own sensitivity to phase differences across its usable frequency range. Typically, choosing a balun with ≤5 degrees of phase imbalance over your application’s operating bandwidth would be a good start. This amount of phase imbalance would add little to the aggregate even-order distortion already existing in your RF signal-chain lineup [2].

Figure 2 shows the difference between the same two matched baluns scenarios, and its impact on even-order distortion using the ADC3669. Notice that the third harmonic distortion (HD3) is relatively the same across frequency and has no significant differences.

Over the years, there have been many attempts to simulate and perfect the balun match. After weeks to months of simulation and trying to understand some level of PCB parasitics, it’s still possible that the match will not work out in your favor when fabricating the PCB design. We suggest starting the design process differently, using the topology shown in Figure 3.

If you’re wondering whether all of this effort and trade-offs are actually worth it, we suggest referring back to Figure 1.