SLYY211 October   2021 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1. 1 Message from the editors
  2. 2 System Design
    1. 2.1 Control
      1. 2.1.1 Open loop versus closed loop
    2. 2.2 Feedback control
      1. 2.2.1 Error ratio
    3. 2.3 Dynamic systems
      1. 2.3.1 First order system
      2. 2.3.2 Second order system
    4. 2.4 System stability
      1. 2.4.1 Gain margin
      2. 2.4.2 Phase margin
    5. 2.5 Timing requirements
      1. 2.5.1 Peak/rise time
      2. 2.5.2 Settling time
      3. 2.5.3 Overshoot
      4. 2.5.4 Damping
      5. 2.5.5 Delay
    6. 2.6 Discrete Time Domain
    7. 2.7 Filters
      1. 2.7.1 Filter Types
      2. 2.7.2 Filter Orders
    8. 2.8 Notes
  3. 3 Controllers
    1. 3.1 Linear PID
    2. 3.2 Linear PI
    3. 3.3 Nonlinear PID
    4. 3.4 2P2Z
    5. 3.5 3P3Z
    6. 3.6 Direct form controllers
      1. 3.6.1 DF11
      2. 3.6.2 DF13
      3. 3.6.3 DF22
      4. 3.6.4 DF23
    7. 3.7 Notes
  4. 4 ADC
    1. 4.1 ADC definitions
    2. 4.2 ADC resolution
      1. 4.2.1 ADC resolution for unipolar
      2. 4.2.2 ADC resolution for differential signals
      3. 4.2.3 Resolution voltage vs. full-scale range
    3. 4.3 Quantization error of ADC
    4. 4.4 Total harmonic distortion (THD)
      1. 4.4.1 Total harmonic distortion (VRMS)
      2. 4.4.2 Total harmonic distortion (dBc)
    5. 4.5 AC signals
    6. 4.6 DC signals
    7. 4.7 Settling time and conversion accuracy
    8. 4.8 ADC system noise
    9. 4.9 Notes
  5. 5 Comparator
    1. 5.1 Basic operation
    2. 5.2 Offset and hysteresis
    3. 5.3 Propagation delay
    4. 5.4 Notes
  6. 6 Processing
    1. 6.1 Data representation
    2. 6.2 Central processing unit
      1. 6.2.1 CPU basics
      2. 6.2.2 CPU pipeline
      3. 6.2.3 Characteristics of a real-time processor
      4. 6.2.4 Signal chain
    3. 6.3 Memory
    4. 6.4 Direct memory access (DMA)
    5. 6.5 Interrupts
    6. 6.6 Co-processors and accelerators
    7. 6.7 Notes
  7. 7 Encoders
    1. 7.1 Encoder definitions
    2. 7.2 Types of encoders
    3. 7.3 Description of encoders
      1. 7.3.1 Linear encoders
      2. 7.3.2 Rotary encoders
      3. 7.3.3 Position encoders
      4. 7.3.4 Optical encoders
    4. 7.4 Absolute Vs incremental encoders
      1. 7.4.1 Absolute rotary encoders
      2. 7.4.2 Incremental encoders
    5. 7.5 Notes
  8. 8 Pulse width modulation (PWM)
    1. 8.1 PWM definitions
    2. 8.2 Duty cycle
    3. 8.3 Resolution
    4. 8.4 Deadband
    5. 8.5 Notes
  9. 9 DAC
    1. 9.1 DAC definitions
    2. 9.2 DAC error
      1. 9.2.1 DAC offset error
      2. 9.2.2 DAC gain error
      3. 9.2.3 DAC zero-code error
      4. 9.2.4 DAC full-scale error
      5. 9.2.5 DAC differential non-linearity (DNL)
      6. 9.2.6 DAC integral non-linearity (INL)
      7. 9.2.7 DAC total unadjusted error (TUE)
    3. 9.3 DAC output considerations
      1. 9.3.1 DAC linear range
      2. 9.3.2 DAC settling time
      3. 9.3.3 DAC load regulation
    4. 9.4 Notes
  10. 10Mathematical models
    1. 10.1 Laplace transforms
    2. 10.2 Transfer function
    3. 10.3 Transient response
    4. 10.4 Frequency response
    5. 10.5 Z-domain
    6. 10.6 Notes
  11. 11Important Notice

9.2.5 DAC differential non-linearity (DNL)

Differential Non-Linearity (DNL) describes the difference between measured versus ideal step sizes between sequential codes. The DAC manual will typically express only the minimum and maximum deviations for the linear region of the transfer function. DNL performance is typically at its worst near the power supply rails due to internal component saturation. Most modern DACs are monotonic, meaning that the output voltage will not decrease when the input code is incremented. Figure 9-6 shows both monotonic and non-monotonic DNL.

GUID-20210830-SS0I-2L0G-R2WD-GVHB8DT69W41-low.gif Figure 9-6 DAC DNL.