SLYY211 October   2021 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1. 1 Message from the editors
  2. 2 System Design
    1. 2.1 Control
      1. 2.1.1 Open loop versus closed loop
    2. 2.2 Feedback control
      1. 2.2.1 Error ratio
    3. 2.3 Dynamic systems
      1. 2.3.1 First order system
      2. 2.3.2 Second order system
    4. 2.4 System stability
      1. 2.4.1 Gain margin
      2. 2.4.2 Phase margin
    5. 2.5 Timing requirements
      1. 2.5.1 Peak/rise time
      2. 2.5.2 Settling time
      3. 2.5.3 Overshoot
      4. 2.5.4 Damping
      5. 2.5.5 Delay
    6. 2.6 Discrete Time Domain
    7. 2.7 Filters
      1. 2.7.1 Filter Types
      2. 2.7.2 Filter Orders
    8. 2.8 Notes
  3. 3 Controllers
    1. 3.1 Linear PID
    2. 3.2 Linear PI
    3. 3.3 Nonlinear PID
    4. 3.4 2P2Z
    5. 3.5 3P3Z
    6. 3.6 Direct form controllers
      1. 3.6.1 DF11
      2. 3.6.2 DF13
      3. 3.6.3 DF22
      4. 3.6.4 DF23
    7. 3.7 Notes
  4. 4 ADC
    1. 4.1 ADC definitions
    2. 4.2 ADC resolution
      1. 4.2.1 ADC resolution for unipolar
      2. 4.2.2 ADC resolution for differential signals
      3. 4.2.3 Resolution voltage vs. full-scale range
    3. 4.3 Quantization error of ADC
    4. 4.4 Total harmonic distortion (THD)
      1. 4.4.1 Total harmonic distortion (VRMS)
      2. 4.4.2 Total harmonic distortion (dBc)
    5. 4.5 AC signals
    6. 4.6 DC signals
    7. 4.7 Settling time and conversion accuracy
    8. 4.8 ADC system noise
    9. 4.9 Notes
  5. 5 Comparator
    1. 5.1 Basic operation
    2. 5.2 Offset and hysteresis
    3. 5.3 Propagation delay
    4. 5.4 Notes
  6. 6 Processing
    1. 6.1 Data representation
    2. 6.2 Central processing unit
      1. 6.2.1 CPU basics
      2. 6.2.2 CPU pipeline
      3. 6.2.3 Characteristics of a real-time processor
      4. 6.2.4 Signal chain
    3. 6.3 Memory
    4. 6.4 Direct memory access (DMA)
    5. 6.5 Interrupts
    6. 6.6 Co-processors and accelerators
    7. 6.7 Notes
  7. 7 Encoders
    1. 7.1 Encoder definitions
    2. 7.2 Types of encoders
    3. 7.3 Description of encoders
      1. 7.3.1 Linear encoders
      2. 7.3.2 Rotary encoders
      3. 7.3.3 Position encoders
      4. 7.3.4 Optical encoders
    4. 7.4 Absolute Vs incremental encoders
      1. 7.4.1 Absolute rotary encoders
      2. 7.4.2 Incremental encoders
    5. 7.5 Notes
  8. 8 Pulse width modulation (PWM)
    1. 8.1 PWM definitions
    2. 8.2 Duty cycle
    3. 8.3 Resolution
    4. 8.4 Deadband
    5. 8.5 Notes
  9. 9 DAC
    1. 9.1 DAC definitions
    2. 9.2 DAC error
      1. 9.2.1 DAC offset error
      2. 9.2.2 DAC gain error
      3. 9.2.3 DAC zero-code error
      4. 9.2.4 DAC full-scale error
      5. 9.2.5 DAC differential non-linearity (DNL)
      6. 9.2.6 DAC integral non-linearity (INL)
      7. 9.2.7 DAC total unadjusted error (TUE)
    3. 9.3 DAC output considerations
      1. 9.3.1 DAC linear range
      2. 9.3.2 DAC settling time
      3. 9.3.3 DAC load regulation
    4. 9.4 Notes
  10. 10Mathematical models
    1. 10.1 Laplace transforms
    2. 10.2 Transfer function
    3. 10.3 Transient response
    4. 10.4 Frequency response
    5. 10.5 Z-domain
    6. 10.6 Notes
  11. 11Important Notice

6.1 Data representation

Table 6-1 Primitive data types.
Type Default Size
Boolean False 1 bit
Byte 0 8 bits
Char \u000 16 bits
Short 0 16 bits
Int 0 32 bits
Long 0 64 bits
Float 0.0f 32 bits
Double 0.0d 64 bits
Note: Not all CPU architectures use the same bit counts to represent primitive data.

For example, C2000 has a 16-bit architecture and does not support 8-bit types. For a list of data types supported by C2000 devices, see the TMS320C28x Optimizing C/C++ Compiler v21.6.0.LTS.

Note: The size of data pointers depends on the architecture.
Table 6-2 Multiplier prefixes and abbreviations.
Multiplier Prefix Abbreviation
10 9 Giga G
10 6 Mega M
10 3 Kilo k
10 - 3 Milli m
10 - 6 Micro u
10 - 9 Nano n
10 - 12 Pico p
10 - 15 Femto f
Table 6-3 ASCII table.
Binary Oct Dec Hex Chr
0100000 040 32 20 Space
0100001 041 33 21 !
0100010 042 34 22 "
0100011 043 35 23 #
0100100 044 36 24 $
0100101 045 37 25 %
0100110 046 38 26 &
0100111 047 39 27 '
0101000 050 40 28 (
0101001 051 41 29 )
0101010 052 42 2A *
0101011 053 43 2B +
0101100 054 44 2C ,
0101101 055 45 2D -
0101110 056 46 2E .
0101111 057 47 2F /
0110000 060 48 30 0
0110001 061 49 31 1
0110010 062 50 32 2
0110011 063 51 33 3
0110100 064 52 34 4
0110101 065 53 35 5
0110110 066 54 36 6
0110111 067 55 37 7
0111000 070 56 38 8
0111001 071 57 39 9
0111010 072 58 3A :
0111011 073 59 3B ;
0111100 074 60 3C <
0111101 075 61 3D =
0111110 076 62 3E >
0111111 077 63 3F ?
1000000 100 64 40 @
1000001 101 65 41 A
1000010 102 66 42 B
1000011 103 67 43 C
1000100 104 68 44 D
1000101 105 69 45 E
1000110 106 70 46 F
1000111 107 71 47 G
1001000 110 72 48 H
1001001 111 73 49 I
1001010 112 74 4A J
1001011 113 75 4B K
1001100 114 76 4C L
1001101 115 77 4D M
1001110 116 78 4E N
1001111 117 79 4F O
1010000 120 80 50 P
1010001 121 81 51 Q
1010010 122 82 52 R
1010011 123 83 53 S
1010100 124 84 54 T
1010101 125 85 55 U
1010110 126 86 56 V
1010111 127 87 57 W
1011000 130 88 58 X
1011001 131 89 59 Y
1011010 132 90 5A Z
1011011 133 91 5B [
1011100 134 92 5C \
1011101 135 93 5D ]
1011110 136 94 5E ^
1011111 137 95 5F _
1100000 140 96 60 `
1100001 141 97 61 a
1100010 142 98 62 b
1100011 143 99 63 c
1100100 144 100 64 d
1100101 145 101 65 e
1100110 146 102 66 f
1100111 147 103 67 g
1101000 150 104 68 h
1101001 151 105 69 i
1101010 152 106 6A j
1101011 153 107 6B k
1101100 154 108 6C l
1101101 155 109 6D m
1101110 156 110 6E n
1101111 157 111 6F o
1110000 160 112 70 p
1110001 161 113 71 q
1110010 162 114 72 r
1110011 163 115 73 s
1110100 164 116 74 t
1110101 165 117 75 u
1110110 166 118 76 v
1110111 167 119 77 w
1111000 170 120 78 x
1111001 171 121 79 y
1111010 172 122 7A z
1111011 173 123 7B {
1111100 174 124 7C |
1111101 175 125 7D }
1111110 176 126 7E ~