Trend toward lower jitter

Lower jitter is necessary for high-speed Ethernet applications such as ToR switches, spine or fabric switches, optical modules, and NICs or SmartNICs. 112-Gbps-lane-speed Ethernet SerDes typically requires 125- or 100-fs 12-kHz to 20-MHz root-mean-square jitter at 156.25 MHz. 224-Gbps Ethernet typically requires 70 fs; future Ethernet clocks should achieve 50-fs maximum jitter or better. TI’s proprietary bulk acoustic wave (BAW) technology provides 65-fs maximum jitter at 156.25 MHz in current TI products. Reference [1] provides more details about BAW technology.

Jitter requirements for PCIe reference clocks are also getting more stringent, especially in PCIe Gen 6, where the modulation scheme changed from non-return-to-zero (NRZ) to pulse amplitude modulation 4-level (PAM-4). Because PAM-4 operates on four levels compared to two levels in NRZ, it requires lower noise from the reference clock. This is also the reason why 56-Gbps PAM-4 Ethernet requires significantly better jitter performance than 28-Gbps NRZ. However, because PCIe compliance defines a noise transfer function to “filter” the jitter, the jitter requirement for PCIe is much more relaxed than Ethernet.