1 ADC Signal-to-Noise Ratio Components

The signal-to-noise ratio (SNR) of the ADC is a key specification. A high number for this specification indicates the ADC can better distinguish the desired input signal from the undesired noise that is also captured during sampling. There are three main contributors to the SNR of an ADC, the quantization and thermal noise of the ADC (does not change with input frequency) and the clock jitter (depends on the frequency). Figure 1-1 shows an example of an ADC thermal noise of 62.5 dBFs and the SNR of the clock (with a jitter, t_{clock_jitter} of 50 fs). The SNR of a clock can be derived from knowing the frequency of the signal and the jitter (discussed in Section 2) with Equation 1:

As the figure illustrates, the high SNR of the ADC is maintained for the low input frequencies, but starts to be dominated by the clock SNR at higher input frequencies.

Now that the impact of clock jitter to the total SNR when the clock has a jitter of 50 fs is known, look at the impact of lower performance clock (with higher jitter). As Figure 1-2 shows, the higher the jitter of the clock, the more severe the effect of degradation in SNR from the clock performance at higher ADC input frequencies. Therefore, it is essential to make sure the clock jitter is the lowest possible, and this specification can be adjusted according to different parameters of a high frequency synthesizer clock source to achieve the optimal low jitter value.