SNAS634B March 2014 – January 2016 LMP92066
PRODUCTION DATA.
PIN | TYPE (1) | DESCRIPTION | ESD STRUCTURES | |
---|---|---|---|---|
NUMBER | NAME | |||
1 | GNDD | G | Lower power rail of the digital I/O |
|
2:3 | DRVEN[1:0] | I | Asynchronous control of the Changeover Switches |
|
4 | VIO | I | Digital I/O power supply rail | |
5 | SDA | I/O | I2C bi-directional data line | |
6 | SCL | I | I2C clock input | |
7:8 | A[1:0] | I | I2C slave address selector |
|
9 | VSSB | P | Output drive lower supply rail |
|
10, 14 | DAC0 DAC1 |
O | DAC0 output |
|
11, 13 | FETDRV0 FETDRV1 |
O | Gate drive of the external FET device | |
12 | GNDA | G | Analog block lower rail |
|
15 | VDDB | P | Output drive upper supply rail |
|
16 | VDD | P | Analog block upper rail |
|
--- | DAP | G | Die Attach Pad. For best thermal, and noise performance it should be soldered to the local system ground pad. |
|