SNAS668E August 2015 – September 2024 LMK03328
PRODUCTION DATA
In case the VDD_IN, VDD_PLL1, VDD_PLL2, and VDD_DIG, and VDDO supplies ramp slowly with a ramp time over 100 ms, TI recommends starting the device POR sequence after all core and output supplies have reached the minimum voltage tolerances (VDD ≥ 3.135 V and VDDO ≥ 1.71 V). This can be realized by delaying the PDN low-to-high transition in a manner similar to the condition detailed in Powering Up From Split-Supply Rails and shown in Figure 10-11.
If a VDD supply can not reach 3.135 V before the PDN low-to-high transition, TI recommends toggling the PDN pin again or chip soft reset bit in R12.7 after all VDD and VDDO supplies reached the minimum tolerances to re-trigger the device POR sequence for normal chip operation.
If only VDDO supplies ramp after the PDN low-to-high transition, issuing a channel reset on any PLL-driven output channel with the PLL SYNC enabled (PLL_SYNC_EN=1) is recommended to provide normal output divider operation without requiring a full chip reset (through the PDN pin or soft reset). A local channel reset can be issued by toggling the corresponding power-down bit or bits in R30 after the VDDO supply has reached 1.71 V. Alternatively, an output SYNC can be issued to reset any SYNC-enabled channel (see Output Synchronization).