SNAS669E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
Input Clock Control
Bit # | Field | Type | Reset | EEPROM | Description | |
---|---|---|---|---|---|---|
[7] | CLKMUX_BYPASS | RW | 0 | Y | Clock Mux Bypass. Controls whether the glitch-less clock mux on the the Primary and Secondary Reference paths is enabled. When CLKMUX_BYPASS is 1 then the clock mux is by-passed. | |
[6:3] | RSRVD | RW | 0x0 | Y | Reserved. | |
[2] | SECONSWITCH | RW | 0 | Y | Secondary Crystal Input Buffer On after Switch. Determines whether the Secondary Crystal Input Buffer remains on after a switch back to the Primary Input. If SECONSWITCH is 0 then the Secomdary Crystal Input Buffer is disabled after a switch back to the Primary input. If SECONSWITCH is 1 then the Secondary Crystal Input Buffer remains active after a switch back to the Primary input. | |
[1] | SECBUFGAIN | RW | 1 | Y | Secondary Input Buffer Gain. | |
SECBUFGAIN | GAIN | |||||
0 | Minimum | |||||
1 | Maximum | |||||
[0] | PRIBUFGAIN | RW | 1 | Y | Primary Input Buffer Gain. | |
PRIBUFGAIN | GAIN | |||||
0 | Minimum | |||||
1 | Maximum |