SNAU259 August   2021 LMK1D1208

 

  1.   Trademarks
  2. 1 Features
  3. 2 General Description
  4. 3 Signal Path and Control Circuitry
  5. 4 Getting Started
  6. 5 Power Supply Connection
  7. 6 Input Clock Selection
    1. 6.1 Differential Input
    2. 6.2 Configuring Single-Ended Input
  8. 7 Output Clock
  9. 8 EVM Board Schematic
  10. 9 REACH Compliance
  11. 10Bill of Materials

3 Signal Path and Control Circuitry

The LMK1D1208 supports single-ended inputs up to 250 MHz and differential inputs up to 2 GHz. Each device provides up to eight LVDS outputs operating at the input frequency.

For more information, see the LMK1D1208 Low Additive Jitter LVDS Buffer data sheet (SNAS815) for details.