SNIS233A February   2024  – July 2024 TMP110

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Temperature Output
      2. 7.3.2 Decoding Temperature Data
      3. 7.3.3 Temperature Limits and Alert
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous-Conversion Mode
      2. 7.4.2 One-Shot Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Bus Overview
      3. 7.5.3 Device Address
      4. 7.5.4 Bus Transactions
        1. 7.5.4.1 Writes
        2. 7.5.4.2 Reads
        3. 7.5.4.3 General Call Reset Function
        4. 7.5.4.4 SMBus Alert Response
        5. 7.5.4.5 Time-Out Function
        6. 7.5.4.6 Coexist on I3C Mixed Bus
  9. 8 Register Map
    1. 8.1 Temp_Result Register (address = 00h) [reset = xxxxh]
    2. 8.2 Configuration Register (address = 01h) [reset = 60A0h]
    3. 8.3 TLow_Limit Register (address = 02h) [reset = 4B00h]
    4. 8.4 THigh_Limit Register (address = 03h) [reset = 5000h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Equal I2C Pullup and Supply Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
      4. 9.2.4 Power Supply Recommendations
    3. 9.3 Layout
      1. 9.3.1 Layout Guidelines
      2. 9.3.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.3.2 Layout Example

There are special considerations that need to be taken for the TMP110 X2SON package. These considerations are due to the center pad being electrically connected to either address or alert (depending on the orderables shown in Table 7-8) and because of the dimensions of the package and the pads. With the address option, the center pad can be directly connected with a trace on the same layer to one of the 4 edge pins for setting the device address as shown in Figure 9-3.

TMP110 ADD0 Pin Layout ExampleFigure 9-3 ADD0 Pin Layout Example

When using the ALERT pin of the device, a 4 mil trace can be routed between pins 1 and 5 or pins 2 and 4. This signal can be either routed out in between the pads or on a different layer using a via within the center pad as shown in Figure 9-4. Both of these methods have constraints that must be considered as explained below. Ultimately, choosing one of these methods depends on the specifications of the board manufacturing process:

  • Option 1 (Routing in between pads): introduces trace clearance and trace width limitations. As the maximum space between pads is 0.26mm (10.2 mil), assuming a trace width of 0.1mm (4 mil) limits the minimum clearance to 0.08mm (3.15 mil).
  • Option 2 (Routing on a different layer using a via): has specific benefits to the user application. For instance, minimum trace clearance and trace width are higher but require a via on the center pad with specific dimensions. The via diameter must be less than 0.305mm (13.78 mil) to keep the via smaller than the center pad and a minimum drill diameter of 0.1mm (4 mil) can be assumed to avoid manufacturing issues. With this scenario, a minimum annular ring width specification of 0.125mm (5 mil) is required: Anullar Ring Width (mm) = (0.305-0.1)/2.
TMP110 ALERT Pin Layout ExampleFigure 9-4 ALERT Pin Layout Example