SNLA132G October   2011  – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview of Internal Test Pattern Generation
    1. 2.1 Color Mode
    2. 2.2 Video Timing Modes
    3. 2.3 Clock Generation
    4. 2.4 Pattern Selection
    5. 2.5 Pattern Inversion
    6. 2.6 Auto-Scrolling
  4. 3Serial Control Bus Registers for Internal Test Pattern Generation
    1. 3.1 Direct Register Map
      1. 3.1.1 Control and Configuration
      2. 3.1.2 Indirect Access Address and Data
      3. 3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source
    2. 3.2 Indirect Register Map
      1. 3.2.1 General Control
      2. 3.2.2 Internal Timing Control
      3. 3.2.3 Auto-Scrolling Control
  5. 4Configuration Examples
    1. 4.1 Auto-Scrolling Configuration
    2. 4.2 Internal Default Timing Configuration
    3. 4.3 Custom Display Configuration
    4. 4.4 1080p60 with External Clock Example Configuration
    5. 4.5 Resolution Readback Example
  6. 5Conclusion
  7. 6References
  8. 7Revision History

7 Revision History

Changes from Revision F (October 2020) to Revision G (November 2020)

  • Fixed typos in the supported devices for PGCDC2 register Go
  • Added recommendation to force single/dual FPD-Link mode when utilizing 800MHz internal base clock on DS90Ux941AS-Q1, DS90Ux949-Q1, DS90Ux949A-Q1, DS90Ux929-Q1, and DS90Ux947-Q1 Go
  • Renamed PATGEN BIST Example to Resolution Readback Example and simplified stepsGo

Changes from Revision E (February 2020) to Revision F (October 2020)

  • Added 800MHz base clock option for DS90Ux949-Q1, DS90Ux949A-Q1, DS90Ux929-Q1, and DS90Ux947-Q1Go
  • Added DS90Ux949-Q1, DS90Ux949A-Q1, DS90Ux929-Q1, and DS90Ux947-Q1 to the supported list for PGCDC2Go
  • Clarified supported devices which can adjust the M clock dividerGo

Changes from Revision D (June 2019) to Revision E (February 2020)

  • Changed text to remove typosGo

Changes from Revision C (June 2013) to Revision D (June 2019)

  • Added 94x devices.Go
  • Added 921/924.Go
  • Edited application report for clarity.Go
  • Clarified supported features differences between 92x devices and between 92x vs. 94x.Go
  • Added 1080p60 target resolution to the Internal Oscillator Frequencies table.Go
  • Clarified clock generation 94x has more capability and also added 800 MHz info for 941AS.Go
  • Added PATGEN Bist Register.Go
  • Added 941AS “M” divider register.Go
  • Clarified target clock frequencies between devices. Go
  • Added missing example code in the custom display example for setting sync polarities and widths.Go
  • Added 94x example code for 1080p with external PCLK.Go
  • Added PATGEN BIST Example section.Go