SNLA261A August   2016  – March 2024 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83825I , DP83826E , DP83826I , DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS , DP83869HM

 

  1.   1
  2.   DP838xx Wake-On-LAN
  3.   Trademarks
  4. 1Introduction
  5. 2Wake-on-LAN
    1. 2.1 WoL – Principles of Operation
      1. 2.1.1 Magic Packet Detection
      2. 2.1.2 Magic Packet Detection with Secure-ON
      3. 2.1.3 Custom Pattern Detection
      4. 2.1.4 WoL - Mechanisms
    2. 2.2 WoL - Implementation
      1. 2.2.1 Magic Packet Detection - Implementation
        1. 2.2.1.1 Example 1 – Pulse Mode Indication on LED_1 (DP83822)
        2. 2.2.1.2 Example 2 – Level Change Mode Indication on COL (DP83822)
        3. 2.2.1.3 Example 3 – Pulse Mode indication on GPIO_1 (DP83867)
      2. 2.2.2 Magic Packet Detection with Secure-ON - Implementation
        1. 2.2.2.1 Example 1 – Pulse Mode Indication on COL with Secure-ON (DP83822)
        2. 2.2.2.2 Example 2 – Level Change Mode Indication on RX_D3 with Secure-ON (DP83822)
        3. 2.2.2.3 Example 3 – Pulse Mode indication on GPIO_1 (DP83869)
      3. 2.2.3 Custom Pattern Detection - Implementation
        1. 2.2.3.1 Example 1 – Pulse Mode Indication on COL with Byte Mask (DP83822)
        2. 2.2.3.2 Example 2 – Pulse Mode Indication on GPIO_0 with Byte Mask (DP83867)
  6. 3Summary
  7. 4Revision History

2.1 WoL – Principles of Operation

Wake-on-LAN (WoL) is a mechanism that maintains full function of the PHY, but allows for an interrupt trigger based on specific frame detection. By using WoL, backend equipment (for example, FPGAs, SoCs, Processors, ASICs, MCUs) can be powered-down until the PHY receives information that passes the specific frame detection criteria. An application solution will need to be created using the PHY's trigger once the frame detection criteria is met.

At the PHY level, an active link with a LP is required and maintained in WoL mode as the backend equipment is powered-down while the PHY is fully functional. When a qualifying frame is received, DP838xx can be configured to either send a level change or pulse indication to the GPIO pins. Additionally, DP838xx allows for interrupt configuration on INT/PWDN_N pin with polarity specification as active HIGH or active LOW.

There are three main WoL functions to allow for user flexibility and security; Magic Packet Detection, Magic Packet Detection with Secure-ON, and Custom Pattern Detection (also known as Pattern Matching).

Table 2-1 indicates which WoL features are supported on which PHYs.

Table 2-1 WoL Features Support on PHYs
Magic Packet DetectionMagic Packet Detection with Secure-ONPattern Matching
DP83822YesYesYes
DP83825YesYesNo
DP83826YesYesNo
DP838671Unicast OnlyUnicast OnlyYes
DP83869YesYesYes
  1. Unicast packets have unique Destination Address fields, as opposed to Broadcast packets which have a Destination Address of FF:FF:FF.