• Menu
  • Product
  • Email
  • PDF
  • Order now

  • DP8382x IEEE 802.3u Compliance and Debug

    • SNLA266B August   2016  – April 2025 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83825I , DP83826E , DP83826I

       

  • CONTENTS
  • SEARCH
  • DP8382x IEEE 802.3u Compliance and Debug
  1.   1
  2.   DP8382x IEEE 802.3u Compliance and Debug
  3.   Trademarks
  4. 1Terminology
  5. 2Standards and System Requirements
    1. 2.1 Standards
    2. 2.2 Test Equipment Suppliers
    3. 2.3 Test Equipment Requirements
  6. 3Ethernet Physical Layer Compliance Testing
    1. 3.1 Standard Test Setup and Procedures
    2. 3.2 100BASE-TX Compliance Testing
      1. 3.2.1 Template (Active Output Interface)
      2. 3.2.2 Differential Output Voltage
      3. 3.2.3 Rise and Fall Time
      4. 3.2.4 Waveform Overshoot
      5. 3.2.5 Jitter
      6. 3.2.6 Duty Cycle Distortion
      7. 3.2.7 Return Loss
    3. 3.3 10BASE-Te Compliance Testing
      1. 3.3.1 Link Pulse
      2. 3.3.2 10BASE-Te Standard
        1. 3.3.2.1 TP_IDL
        2. 3.3.2.2 MAU, Internal
        3. 3.3.2.3 Jitter With TPM
        4. 3.3.2.4 Jitter Without TPM
        5. 3.3.2.5 Differential Voltage
        6. 3.3.2.6 Common-Mode Voltage
        7. 3.3.2.7 Return Loss
        8. 3.3.2.8 Harmonic Content
  7. 4How to Tune DP83825 VoD Swing
    1. 4.1 Example of Tuning DP83825 VoD Swing
  8. 5IEEE802.3u Compliance Testing Scripts for the DP8382x
  9. 6References
  10. 7Revision History
  11. IMPORTANT NOTICE
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

Application Note

DP8382x IEEE 802.3u Compliance and Debug

Abstract

DP83822, DP83825, and DP83826 (referred throughout this document as DP8382x) devices are a family of 10/100Mbps Industrial Ethernet physical layer (PHY) that is compliant to IEEE 802.3. This application note discusses 100BASE-TX and 10BASE-Te compliance testing and the procedures for operating the DUT for these tests.

Trademarks

Tektronix® is a registered trademark of Tektronix, Inc.

Spirent® is a registered trademark of Spirent Communications plc.

Agilent® is a registered trademark of Agilent Technologies, Inc.

Keysight® is a registered trademark of Keysight Technologies, Inc.

Rohde & Schwarz® is a registered trademark of Rohde & Schwarz GmbH & Co. KG.

LeCroy® is a registered trademark of Teledyne LeCroy, Inc..

All trademarks are the property of their respective owners.

1 Terminology

Table 1-1 provides a list of terminology that is used throughout this application note.

Table 1-1 Terminology
ACRONYM DEFINITION
DUT Device Under Test
LP Link Partner
PHY Physical Layer Transceiver
SMI Serial Management Interface
IPG Inter-Packet Gap
FLP Fast Link Pulse
NLP Normal Link Pulse
TX Transmit – Digital Pins
RX Receive – Digital Pins
TD Transmit – Analog Pins
RD Receive – Analog Pins
AVD Analog Supply
CT Magnetic Center Tap
VDDIO Digital Supply
BIST Built-In Self-Test
TPM Twisted Pair Model
AOI Active Output Interface
AFE Analog Front-End

MDI

Media Dependent Interface

MDIX

Crossover version of Media Dependent Interface

VoD

Differential Output Voltage

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale