SNLA308A April   2019  – October 2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Superframe Requirements
    1. 2.1 Left/Right 3D Format
    2. 2.2 Alternate Line 3D Format
    3. 2.3 Alternate Pixel 3D Format
  4. 3 Video Processing Status Monitoring
    1. 3.1 VIDEO_3D_STS Register (Address = 58h) [reset = 0h]
  5. 4 Superframe Splitting
  6. 5 Frame Cropping
    1. 5.1 Cropping Control Registers
      1. 5.1.1 CROP_START_X0_CROP_START_X0_P1 Register (Address = 36h) [reset = 0h]
      2. 5.1.2 CROP_START_X1_CROP_START_X1_P1 Register (Address = 37h) [reset = 0h]
      3. 5.1.3 CROP_STOP_X0_CROP_STOP_X0_P1 Register (Address = 38h) [reset = 0h]
      4. 5.1.4 CROP_STOP_X1_CROP_STOP_X1_P1 Register (Address = 39h) [reset = 0h]
      5. 5.1.5 CROP_START_Y0_CROP_START_Y0_P1 Register (Address = 3Ah) [reset = 0h]
      6. 5.1.6 CROP_START_Y1_CROP_START_Y1_P1 Register (Address = 3Bh) [reset = 0h]
      7. 5.1.7 CROP_STOP_Y0_CROP_STOP_Y0_P1 Register (Address = 3Ch) [reset = 0h]
      8. 5.1.8 CROP_STOP_Y1_CROP_STOP_Y1_P1 Register (Address = 3Dh) [reset = 0h]
    2. 5.2 Cropping Options
  7. 6 Splitter Mode Pixel Clocks
    1. 6.1 SPLIT_CLK_CTL0_SPLIT_CLK_CTL0_P1 Register (Address = 3Eh) [reset = 81h]
    2. 6.2 SPLIT_CLK_CTL1_SPLIT_CLK_CTL1_P1 Register (Address = 3Fh) [reset = 2h]
  8. 7 Programming Example
  9. 8 Summary
  10. 9 References
  11. 10Handling Interrupts With the DS90Ux941AS-Q1
    1. 10.1 Interrupt Control and Status (INTB and REM_INTB Pin)
    2. 10.2 Handling Interrupts in Splitter Mode Using Remote Interrupt Pin (REM_INTB)
    3. 10.3 REM_INTB_CTRL Register (Address = 30h) [reset = 0h]
  12. 11High-Speed GPIO Operation in Splitter Mode
    1. 11.1 Introduction
    2. 11.2 High-Speed Control Configuration
      1. 11.2.1 DES_CAP1 Registers (Address = 20h)
      2. 11.2.2 DES_CAP2 Registers (Address = 21h)
    3. 11.3 Back Channel Frequency Configuration
    4. 11.4 Splitter Mode GPIO
    5. 11.5 GPIO_0_Config Register (Address = Dh) [reset = 20h]
    6. 11.6 GPIO_1_and_GPIO_2_Config Register (Address = Eh) [reset = 0h]
    7. 11.7 GPIO_3_Config Register (Address = Fh) [reset = 0h]
  13.   Revision History

11.2.1 DES_CAP1 Registers (Address = 20h)

DES_CAP1 is described inTable 11-1

Table 11-1 DES_CAP1 Register Field Description
BitFieldTypeResetDescription
7FREEZE_DES_CAP
FREEZE_DES_CAP_1		R0hIf PORT1_SEL is set, this register indicates Port1 Capabilities
Freeze Deserializer Capabilities
Prevent auto-loading of the Deserializer Capabilities by the Bidirectional Control Channel. The Capabilities are frozen at the values written in registers 0x20 and 0x21.
6HSCC_MODE_0
_HSCC_MODE_P1_0		R/W0hHigh-Speed Control Channel bit 0
Lowest bit of the 3-bit HSCC indication. The other 2 bits are contained in Deserializer Capabilities 2. This field automatically configured by Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel.
5RESERVEDR0hReserved
4RESERVEDR0hReserved
3DUAL_LINK_CAP
DUAL_LINK_CAP_1		R/W0hDual link Capabilities
Indicates if the Deserializer is capable of dual link operation.
This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel..
2DUAL_CHANNEL_CAP
DUAL_CHANNEL_CAP_1		R/W0hDual Channel 0/1 Indication
In a dual-link capable device, indicates if this is primary or secondary channel.
0: Primary channel (channel 0)
1: Secondary channel (channel 1)
This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel.
1VID_24B_HD_AUD
VID_24B_HD_AUD_P1		R/W0hDeserializer supports 24-bit video concurrently with HD audio
This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel.
0DES_CAP_FC_GPIO
DES_CAP_FC_GPIO_P1		R/W0hDeserializer supports GPIO in the Forward Channel Frame
This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel.