SNLA308A April 2019 – October 2020 DS90UB941AS-Q1 , DS90UH941AS-Q1
SPLIT_CLK_CTL0_SPLIT_CLK_CTL0_P1 is described in Table 6-1.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SPLIT_CLK_DIV_EN_SP LIT_CLK_DIV_EN_P1 | R/W | 1h | Splitter Mode Clock Control Register 0. This controls the selected FPD-Link III port. Splitter mode clock divider enable. This register enables the splitter mode clock divider. In splitter mode, if this register is set to 0, the pixel clock for splitter operation is disabled. The divider should be disabled prior to changing the Splitter Divider settings, SPLIT_CLK_SEL, SPLIT_CLK_DIV_M, and SPLIT_CLK_DIV_N. In addition, changes to divider settings must only be done when the DSI input is disabled to ensure proper mode transition. These values are ignored if Splitter mode is disabled. This controls the selected FPD-Link III port. |
6-5 | SPLIT_CLK_SEL | R/W | 0h | Splitter mode clock select. This register selects the clock source for the FPD-Link III transmit side of the splitter operation for the selected port. 00 : Input pixel clock divided by 2 (default). 01 : M/N divider from the DPHY input clock. 10 : M/N divider from the external clock on the REFCLK0 pin. 11 : M/N divider from the external clock on the REFCLK1 pin. |
4-0 | SPLIT_CLK_DIV_M_SPLI T_CLK_DIV_M_P1 | R/W | 1h | Splitter mode clock divider M value. This register controls the M setting for the M/N divider used to generate the splitter mode pixel clock from the selected input clock. The default settings for M/N provide a half clock frequency normally required for splitting symmetric video. These values are ignored if Splitter mode is disabled. This controls the selected FPD-Link III port. |