SNLA344C March   2022  – October 2023 DP83826E , DP83826I

 

  1.   1
  2.   How and Why to Use the DP83826E for EtherCAT Applications
  3.   Trademarks
  4. 1Introduction
  5. 2EtherCAT® Specification Requirements and Recommendations
  6. 3Different Methods of Setting up the PHY
    1. 3.1 Using Strap Configuration to Set Up DP83826 PHY for EtherCAT® Configuration
      1. 3.1.1 Strapping Options
    2. 3.2 Using Serial Management Interface to Setup DP83826 PHY
      1. 3.2.1 Programming Options
  7. 4References
  8. 5Revision History

2 EtherCAT® Specification Requirements and Recommendations

Another reference to look into is for EtherCAT PHY specification. This is found in the Application Note – PHY Selection Guide on the EtherCAT® home page. Table 2-1 shows a copy of that document version 2.6 (2017-10-04) compared with DP83826's compliance to the requirement. Additional data sheet reference for DP83826 is provided.
Table 2-1 PHY Selection Guide
PHY Selection Guide Requirement DP83826 Compliance to Requirement Data Sheet Reference Sections(1)
The PHYs have to comply with IEEE 802.3 100Base-TX or 100Base-FX. DP83826 is IEEE 802.3 compliant 9.1
The PHYs have to support 100 Mbit/s Full Duplex links. DP83826 supports full duplex operation for both 10Mbit/s and 100Mbit/s 9.5.1 ANAR (0x4)
The PHYs have to provide an MII (or RMII/RGMII) interface. DP83826 provides a MII and RMII (2) interface connection

9.1, 8.6 (Latency Timing)
The PHYs have to use auto-negotiation in 100Base-TX mode. DP83826 has an Auto-negotiation feature which is strap-controlled 9.3.1, 9.4
The PHYs have to support the MII management interface. DP83826 supports serial management interface (SMI) up to a maximum clock rate of 24 MHz 9.3.11
The PHYs have to support MDI/MDI-X auto-crossover in 100Base-TX mode. DP83826 supports this via Auto-MDIX feature 9.3.2, 9.5 PHYCR (0x19)
PHY link loss reaction time (link loss to link signal/LED output change) has to be faster than 15 μs to enable redundancy operation. DP83826 has Fast link-Drop functionality, called "FLD", which shortens the observation window to 10 μs before enabling the link loss indication 8.6 (Link Up Timing), 9.3.16.2
The PHYs must not modify the preamble length. DP83826 does not modify the preamble length N/A
The PHYs must not use IEEE802.3az Energy Efficient Ethernet. DP83826 supports the IEEE802.3az standard. This feature is disabled by default 9.3.3.1
The PHYs must offer the RX_ER signal (MII/RMII) or RX_ER as part of the RX_CTL signal (RGMII). DP83826 supports MII/RMII with standard interface including the RX_ER signal 9.3.9, 9.3.10
The PHYs have to provide a signal indicating a 100 Mbit/s (Full Duplex) link, typically a configurable LED output. The signal polarity is active low or configurable for some ESCs. DP83826 has four (3) (4) possible programmable LED outputs which can each show 100 Mbit/s (Full Duplex) link. 9.3.17, 9.5 MLEDCR (0x25), LEDX_GPIO_CFG (0x303 - 0x306), and LEDCFG (0x460)
The PHY addresses should be equivalent to the logical port number (0–3). Some ESCs also support a fixed offset (for example, offset 16, PHY addresses are logical port number plus 16: 16-19), an arbitrary offset, or even individually configurable PHY addresses. If none of these possibilities can be used, the PHY address should be configured to logical port number plus 1 (1–4), although some features (for example, Enhanced Link Detection) cannot be used in this case, because apart from the optional configurable PHY address offset, the PHY addresses are hard-coded inside the ESCs. DP83826 has eight PHY addresses which can be set using strap resistors 9.4.1.1.1, 9.4.1.2.1
PHY configuration must not rely on configuration via the MII management interface, that is, required features have to be enabled after power-on, for example, by default or by strapping options. PHY startup should not rely on MII management interaction, that is MDC clocking, since many ESCs do not communicate with the PHY via management interface unless the EtherCAT® master requests this (only the EtherCAT® IP Core with MI Link detection and configuration will communicate without master interaction). DP83826 has bootstrap configurations for setting the PHY in a specific mode which allows EtherCAT® communication. 5, 9.4.1.1
All PHYs connected to one ESC and the ESC itself must share the same clock source, so a TX FIFO can be omitted. This can be achieved by sourcing the PHYs from an ESC clock output or by sourcing the PHYs and the ESC from the same quartz oscillator. The ESC10/20 uses TX_CLK as a clock source, both PHYs have to share the same quartz oscillator. This can be resolved using an external clock source for DP83826 as long as specification for this clock source is followed. DP83826 also has a clock out option which can be used to source second PHY's clock 8.6 (25MHz or 50MHz Input Clock Tolerance), 9.3.8
The phase offset between TX_CLK and the clock input of the PHYs is compensated inside the ESC, either manually by configuration or automatically. The clock period cannot change between the devices since the PHYs and the ESC have to share the same clock source. This requirement is for the MAC interface and is PHY independent N/A
Manual TX Shift compensation: ET1100, ET1200, and IP Core provide a TX Shift configuration option (configurable TX_EN/TXD signal delay by 0/10/20/30 ns) which is used for all MII ports. Thus, all PHYs connected to one ESC must have the same fixed phase relation between TX_CLK and the clock input of the PHY, with a tolerance of ±5 ns. The phase relation has to be the same each time the PHYs are powered on, or establish a link. As the ESC10/20 use TX_CLK as device clock source, configuration is not necessary, but the requirements for manual TX Shift compensation have to be fulfilled anyway. DP83826 has a nominal ±2 ns tolerance of this specification, with maximum of ±4 ns. 8.6 (Latency Timing)
Automatic TX Shift compensation: The IP Core supports automatic TX Shift compensation individually for each port. With automatic TX Shift compensation, the PHYs are not required to have the same fixed phase relation each time they are powered on, or establish a link. This requirement is for the MAC interface and is PHY independent N/A
(2) Notice that typical latency of RMII interface (in general) is higher than the EtherCAT® specified latency requirement
(3) DP83826 has different LED pins available depending on the mode DP83826 is in: Enhanced or Basic.
(4) LED3 functionality is available in RMII mode only.

Table 2-2 shows a copy of Application Note – PHY Selection Guide document version 2.6 (2017-10-04) compared with DP83826's compliance to the recommendation. Additional data sheet reference for DP83826 is provided.

Table 2-2 PHY Selection Guide
PHY Selection Guide Recommendation DP83826 Compliance to Recommendation Data Sheet Reference Sections
Receive and transmit delays should be deterministic, and as low as possible. DP83826 RX and TX signal latency based on the MII interface is ±2 ns 8.6(Latency Timing)
Maximum cable length should be ≥ 120 m to maintain a safety margin if the standard maximum cable length of 100 m is used. DP83826 has been tested to be above 150 m 1
ESD tolerance should be as high as possible (4 kV, or better) DP83826 has been tested without external protection to withstand ESD Ratings based on HBM for MDI pins (±5 kV) and all pins other pins (±2 kV) and on CDM for all pins ±0.75 kV. With external protection IEC 61000-4-2 ESD: ±8 kV contact, ±15 kV air and for IEC 61000-4-4 EFT: ±4 kV @ 5 kHz and 100 kHz. 8.2, 1
Baseline wander should be compensated (the PHYs should cope with the ANSI X3.263 DDJ test pattern for baseline wander measurements at maximum cable length) DP83826 has been tested and shows excellent performance compensating the baseline wander. It is recommended that register 0xB[0] is set to 0, otherwise the baseline wander test will fail because the PHY drops the link as to the energy detection mechanism is seeing the test pattern as a link drop.

9.5.1CR3 (0xB),

9.3.16.2
The PHYs should detect link loss within the link loss reactiont ime of 15 μs also if only one of the RX+ and RX- lines gets disconnected. Fast Link-Drop functionality shortens the observation window to 10 μs before enabling the link loss indication 8.6(Fast Link Pulse Timing), 9.3.16.2
The PHYs should maintain the link state regardless of the received symbols, as long as the symbols are valid. The PHY will be able to maintain the link state so longas the fast link drop functionality determines no reason to drop link 9.3.16.2
Ethernet PHYs for 100Base-FX should implement Far- End-Fault(FEF) completely (generation and detection). DP83826 is a 100Base-TX PHY and does not support 100Base-FX 1
MDC should not incorporate pullup, pulldown resistors, as this signal is used as a configuration input signal by some ESCs. MDC having internal pulldown resistor (nominal 10 kΩ),this has to be taken into account when defining pullup 8.5, 6, 7
Restriction of Auto-negotiation advertisement to 100 Mbit/s/ Full Duplex is desirable (configured by hardware strapping options). Advertisement can be set by strap configuration 9.4.1
Power consumption should be as low as possible. Worst-case power consumption for MII interfaced 100BaseTX is a total of 67 mA at 3.3V VDDA and VDDIO levels 8.5 (Power consumption [Active mode worst case, …..])
I/O voltage: 3.3 V should be supported for current ASIC and FPGA ESCs, an additional 2.5 V, 1.8 V I/O support is recommended for recent FPGA ESCs. DP83826 supports 3.3 V and 1.8 V I/O voltage 8.3, 9.1
Single power supply according to I/O voltage. Support single power supply at 3.3 V 8.3, 9.1
The PHY should use a 25-MHz clock source (quartz oscillator or ESC output). The DP83826 supports Crystal and oscillator inputs

10.2.4.1(25MHz Input

Clock Tolerance)
Industrial temperature range should be supported. DP83826 supports a temperature range from –40 to 105°C 8.3