SNLA356 September   2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2MIPI DSI Source Requirements
    1. 2.1 Supported DSI Modes
    2. 2.2 Clocking Rates and Clock Type
    3. 2.3 Blanking or Low Power Modes (BLLP)
    4. 2.4 DSI Packet Timing
      1. 2.4.1 Non-Burst Mode With Sync Pulses
      2. 2.4.2 Non-Burst Mode With Sync Events
      3. 2.4.3 Burst Mode
  5. 3Bring-Up and Debug Flow
  6. 4Example Bringup Scenarios
    1. 4.1 Discontinuous Clock
    2. 4.2 Missing Periodic Low Power Transitions
    3. 4.3 Incorrect DSI Packet Timing
    4. 4.4 THS-SKIP Configuration
    5. 4.5 End of Transmission Packets (EoTp)
    6. 4.6 Configuration of Sync Width for Event Mode/Burst Mode
  7. 5Summary
  8. 6References

4.6 Configuration of Sync Width for Event Mode/Burst Mode

As described in Section 2.4.2, DSI Non-Burst Mode with Sync Events, and Burst Mode configurations do not utilize horizontal or vertical sync end packets to convey DPI timing to the sink. When these modes are used with DS90UB941AS-Q1, it is required to configure the horizontal and vertical sync widths for the video through the device registers. Without configuring desired sync widths and enabling Event Mode, the display output timing may not meet expectations.

Symptoms:

  • Black screen
  • Jittering/flickering screen
  • Horizontal or vertical rollover

Resolution:

If the DSI source is configured for Event Mode or Burst Mode, first set DSI_SYNC_PULSES = 0 in the DSI_CONFIG_0 register. This will inform the DS90UB941AS-Q1 receiver that it should expect only horizontal/vertical sync start packets, and enable override controls for HSYNC and VSYNC signal generation.

Next, set the DSI_HSW_CFG_HI/DSI_HSW_CFG_LO and DSI_VSW_CFG_HI/DSI_VSW_CFG_LO registers to the desired parameters for the video signal. The horizontal/vertical front porch widths will be defined by the number or pixels/lines following the active data to the start of the HSS or VSS signals.

Example Source Signal:

  • HACT = 1920
  • HFP = 92
  • HTOTAL = 2088
  • VACT = 1080
  • VFP = 35
  • VTOTAL = 1150

Desired Sync Widths:

  • HSYNC = 14 pixels = 0x0E
  • VSYNC = 2 lines = 0x02

Set the DS90UB941AS-Q1 indirect DSI registers:

  1. DSI_HSYNC_WIDTH_HI = 0x00
  2. DSI_HSYNC_WIDTH_LO = 0x0E
  3. DSI_VSYNC_WIDTH_HI = 0x00
  4. DSI_VSYNC_WIDTH_LO = 0x02

First, select the DSI indirect registers corresponding to the desired DSI port:

  1. Write 0x40 = 0x04 for DSI Port 0 or 0x40 = 0x08 for DSI Port 1.
  2. Write 0x41 = 0x30 (DSI_HSW_CFG_HI).
  3. Write 0x42 = 0x00.
  4. Write 0x41 = 0x31 (DSI_HSW_CFG_LO).
  5. Write 0x42 = 0x0E.
  6. Write 0x41 = 0x32 (DSI_VSW_CFG_HI).
  7. Write 0x42 = 0x00.
  8. Write 0x41 = 0x33 (DSI_VSW_CFG_LO).
  9. Write 0x42 = 0x02.

The HBP and VBP signals will be automatically generated based on the number of total pixels/lines, the HFP/VFP widths, and the sync signal override widths:

Equation 15. HBP = HTOTAL - HACT - HFP - HSYNC = 2088 - 1920 - 92 - 14 = 62 pixels
Equation 16. VBP = VTOTAL - VACT - VFP - VSYNC = 33 lines