SNLA371B December 2020 – February 2024 DP83TG720R-Q1 , DP83TG720S-Q1
Sequence | Description | Register Read/Write |
---|---|---|
Step 1: For DP83TG720 as master | Force the link-down by writing register and enable link-partner to go silent. Wait for ~1s after register write. In case of valid open and short cable faults, TDR will still work fine without step 1. For good cable case, TDR register 0x001E may show Fail on bypassing this step. | Write register[0x0576] = 0x0400 |
Step 1: For DP83TG720 as slave | Link-partner should be made silent. In case of valid open and short cable faults, TDR will still work fine without step 1. For good cable case, TDR register 0x001E may show Fail on bypassing this step. | |
Step 2 | TDR configuration: Pre-run | reg[0x0301] = 0xA008 reg[0x0303] = 0x0928 reg[0x0304] = 0x0004 reg[0x0405] = 0x6400 reg[0x083F] = 0x3003 |
Step 3 | Start TDR | 0x001E[15] = 1 |
Step 4 | Wait for 100ms (should be sufficient for TDR to converge for maximum cable length) | |
Step 5 | Read 0x001E[1:0] = [TDR done : TDR fail]. Value should be [1,0]. Fault type/locations are valid only if this correct value is read. Value other than [1,0] will mean that there is some noise/signal on the line which is causing TDR to fail. | |
Step 6 | Fault type and location is read. | Read register 0x030F for fault status and fault type. Refer to Table 7-2 |
Register Bits | Description |
---|---|
[1:0] |
|
[3:2] | Reserved |
[7:4] |
|
[13:8] |
|
[15:14] | Reserved |