SNLA371B December   2020  – February 2024 DP83TG720R-Q1 , DP83TG720S-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Hardware Configuration
    1. 2.1 Schematic
  6. 3 Software Configuration
  7. 4 Testing PMA
    1. 4.1 PMA Testing Procedure
  8. 5 Testing IOP: Link-up and Link-down
    1. 5.1 IOP Testing Procedure
  9. 6 Testing SQI
    1. 6.1 SQI Testing Procedure
    2. 6.2 Mapping SQI with Link Quality
  10. 7 Testing TDR
    1. 7.1 TDR Testing Procedure
  11. 8 Testing EMC/EMI
  12. 10Revision History

4.1 PMA Testing Procedure

Note:
  • Before programming any of the test modes, DP83TG720 should be loaded with the respective initialization register configuration (master or slave) as described in earlier section.
  • Test mode 1 requires link to be established between DUT and link-partner, hence register [0x0001] should read as 0x0145 before running the test.
Table 4-1 Programming PMA Test Modes
Test Mode MMD Register Value
Test Mode 1: Tx_Tclk 125MHz on CLKOUT pin. x01 0x0904 0x2000
Test Mode 2 x01 0x0904 0x4000
Test Mode 4: Tx_Tclk 125MHz on CLKOUT pin. x01 0x0904 0x8000
x1F 0x0453 0x0019
Test Mode 5 x01 0x0904 0xA000
Test Mode 6 x01 0x0904 0xC000
Test Mode 7 x01 0x0904 0xE000