SNLA371B December   2020  – February 2024 DP83TG720R-Q1 , DP83TG720S-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Hardware Configuration
    1. 2.1 Schematic
  6. 3 Software Configuration
  7. 4 Testing PMA
    1. 4.1 PMA Testing Procedure
  8. 5 Testing IOP: Link-up and Link-down
    1. 5.1 IOP Testing Procedure
  9. 6 Testing SQI
    1. 6.1 SQI Testing Procedure
    2. 6.2 Mapping SQI with Link Quality
  10. 7 Testing TDR
    1. 7.1 TDR Testing Procedure
  11. 8 Testing EMC/EMI
  12. 10Revision History

3 Software Configuration

This section contains the register settings of DP83TG720 used during tests in different OA compliance test houses. Most of these register settings are to take care of the margins during EMC/EMI testing. We recommend these settings as the minimum requirement. Further parameters are available to be programmed if required by system or board level constraints.

Table 3-1 Master Mode Configuration
MMDRegisterDefaultOptimizedDescription
1fx001fx0000x8000hard reset
1fx0573x0000x0101

to not let the phy start the link-up procedure

( till full configuration is written)

01x0834xC001xC001

to configure phy in master mode

(if not done through straps already)

1fx0405x6400x5800DSP settings for margins during OA EMC MDI emission test
1fx08ADx3051x3C51DSP settings for margins during OA EMC level-4 immunity test
1fx0894x5FF7x5DF7DSP settings for margins during OA EMC level-4 immunity test
1fx08A0x09F7x09E7DSP settings for margins during OA EMC level-4 immunity test
1fx08C0x1500x4000DSP settings for margins during OA EMC level-4 immunity test
1fx0814x1027x4800DSP settings for margins during OA EMC level-4 immunity test
1fx080Dx2ABFx2EBFDSP settings for margins during OA EMC level-4 immunity test
1fx08C1x0800x0B00DSP settings for margins during OA EMC level-4 immunity test
1fx087Dx0000x0001DSP settings for margins during OA EMC level-4 immunity test
1fx082Ex0000x0000DSP settings for margins during OA EMC level-4 immunity test
1fx0837x0000x00F4DSP settings for margins during OA EMC level-4 immunity test
1fx08BEx0000x0200DSP settings for margins during OA EMC level-4 immunity test
1fx08C5x0000x4000DSP settings for margins during OA EMC level-4 immunity test
1fx08C7x0000x2000DSP settings for margins during OA EMC level-4 immunity test
1fx08B3x0000x005ADSP settings for margins during OA EMC level-4 immunity test
1fx08B4x0000x005ADSP settings for margins during OA EMC level-4 immunity test
1fx08B0x0203x0202DSP settings for margins during OA EMC level-4 immunity test
1fx08B5x0000x00EADSP settings for margins during OA EMC level-4 immunity test
1fx08BAx0000x2828DSP settings for margins during OA EMC level-4 immunity test
1fx08BBx0000x6828DSP settings for margins during OA EMC level-4 immunity test
1fx08BCx0000x0028DSP settings for margins during OA EMC level-4 immunity test
1fx08BFx0000x0000DSP settings for margins during OA EMC level-4 immunity test
1fx08B1x0014x0014DSP settings for margins during OA EMC level-4 immunity test
1fx08B2x0008x0008DSP settings for margins during OA EMC level-4 immunity test
1fx08ECx0006x0000DSP settings for margins during OA EMC level-4 immunity test
1fx08C8x0000x0003DSP settings for margins during OA EMC level-4 immunity test
1fx08BEx0000x0201DSP settings for margins during OA EMC level-4 immunity test
1fx042Bx0000x0018Setting for further reduction of Sgmii jitter.
1fx018C0x0000x0001

to bring phy out of non-autonomous mode

( only if phy is strapped in non-auto mode)

1fx001fx0000x4000soft reset
1fx05730x0000x0001

to let phy start the link-up procedure

(after above configuration is done).

1fx056Ax1F49x5F41to start the send-s detection during link-up sequence
Table 3-2 Slave Mode Configuration
MMDRegisterDefaultOptimizedDescription
1fx001fx0000x8000hard reset
1fx0573x0000x0101

to not let the phy start the link-up procedure

( till full configuration is written)

01x0834x8001x8001

to configure phy in slave mode

(if not done through straps already)

1fx0894x5FF7x5DF7DSP settings for margins during OA EMC MDI emission test
1fx056Ax1F49x5F40DSP settings for margins during OA EMC level-4 immunity test
1fx0405x6400x5800DSP settings for margins during OA EMC level-4 immunity test
1fx08ADx3051x3C51DSP settings for margins during OA EMC level-4 immunity test
1fx0894x5FF7x5DF7DSP settings for margins during OA EMC level-4 immunity test
1fx08A0x09F7x09E7DSP settings for margins during OA EMC level-4 immunity test
1fx08C0x1500x4000DSP settings for margins during OA EMC level-4 immunity test
1fx0814x1027x4800DSP settings for margins during OA EMC level-4 immunity test
1fx080Dx2ABFx2EBFDSP settings for margins during OA EMC level-4 immunity test
1fx08C1x0800x0B00DSP settings for margins during OA EMC level-4 immunity test
1fx087Dx0000x0001DSP settings for margins during OA EMC level-4 immunity test
1fx082Ex0000x0000DSP settings for margins during OA EMC level-4 immunity test
1fx0837x0000x00F4DSP settings for margins during OA EMC level-4 immunity test
1fx08BEx0000x0200DSP settings for margins during OA EMC level-4 immunity test
1fx08C5x0000x4000DSP settings for margins during OA EMC level-4 immunity test
1fx08C7x0000x2000DSP settings for margins during OA EMC level-4 immunity test
1fx08B3x0000x005ADSP settings for margins during OA EMC level-4 immunity test
1fx08B4x0000x005ADSP settings for margins during OA EMC level-4 immunity test
1fx08B0x0203x0202DSP settings for margins during OA EMC level-4 immunity test
1fx08B5x0000x00EADSP settings for margins during OA EMC level-4 immunity test
1fx08BAx0000x2828DSP settings for margins during OA EMC level-4 immunity test
1fx08BBx0000x6828DSP settings for margins during OA EMC level-4 immunity test
1fx08BCx0000x0028DSP settings for margins during OA EMC level-4 immunity test
1fx08BFx0000x0000DSP settings for margins during OA EMC level-4 immunity test
1fx08B1x0014x0014DSP settings for margins during OA EMC level-4 immunity test
1fx08B2x0008x0008DSP settings for margins during OA EMC level-4 immunity test
1fx08ECx0006x0000DSP settings for margins during OA EMC level-4 immunity test
1fx08C8x0000x0003DSP settings for margins during OA EMC level-4 immunity test
1fx08BEx0000x0201DSP settings for margins during OA EMC level-4 immunity test
1fx042Bx0000x0018Setting for further reduction of Sgmii jitter.
1fx082Dx0B8Fx120FSetting for extending ppm tolerance between master and slave device's reference clock
1fx0888x05B8x0438Setting for extending ppm tolerance between master and slave device's reference clock
1fx0824x15E0x09E0Setting for extending ppm tolerance between master and slave device's reference clock
1fx056Ax1F49x5F40to avoid send-s detection till the configuration is done
1fx018Cx0000x0001

to bring phy out of non-autonomous mode

( only if phy is strapped in non-auto mode)

1fx001fx0000x4000soft reset
1fx0573x0000x0001

to let phy start the link-up procedure

(after above configuration is done).

1fx056Ax1F49x5F41to start the send-s detection during link-up sequence
Note: Sequence of above register writes is important. For both master and slave configuration all the DSP settings are in-between the writes to register 0x0573 and 0x056A. This is to make sure that the link-up sequence does not start before the full configuration is written.