SNLA371B December   2020  – February 2024 DP83TG720R-Q1 , DP83TG720S-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Hardware Configuration
    1. 2.1 Schematic
  6. 3 Software Configuration
  7. 4 Testing PMA
    1. 4.1 PMA Testing Procedure
  8. 5 Testing IOP: Link-up and Link-down
    1. 5.1 IOP Testing Procedure
  9. 6 Testing SQI
    1. 6.1 SQI Testing Procedure
    2. 6.2 Mapping SQI with Link Quality
  10. 7 Testing TDR
    1. 7.1 TDR Testing Procedure
  11. 8 Testing EMC/EMI
  12. 10Revision History

5.1 IOP Testing Procedure

Start of measurement:

For the IOP tests measuring link-up time either after power-up or after hardware reset, it is important to start the measurement of link-up time after the initialization configuration is loaded back into DP83TG720. As the configuration is loaded into the PHY by a controller, we recommend the controller to give an indication (a software bit or an IO state) after the last configuration register is written. This indicator going high is the start of measurement of link-up time.

Status to be poled:

Link-status is indicated by bit 15 of register 0x0180: 1 = link-up; 0 = link-down. This should be poled to indicate the event of link-up or link-down during these tests.

Note: If system desires no automatic link-up after power-up (link to only happen after writing the initialization script), managed mode of DP83TG720 should be used by using strap on pin LED_1.