Before discussing the concept of Eye Scan, it is important to understand the concept of Lane Margining at the Receiver (commonly referred to as Lane Margining) in PCIe and how it is used as a metric for signal quality. Lane Margining allows for a user or system to determine how much margin or “cushion” is available on each PCIe lane at each lane’s receiver. The receiver samples the incoming PCIe signal at its receiver at various points in the signal eye, typically beginning at the center of the eye (0 mV, 0 UI offset) and incrementally stepping up or down (voltage) and left or right (UI/time) until a set bit error rate (BER) threshold is reached at the sampling point. After stepping in each direction (up and down for voltage, left and right for UI/time), available lane margin can be determined based on the number of steps taken in each direction before the BER threshold was reached. For example, if the lane margining algorithm samples at steps of 5 mV and 0.02 UI, a lane margining result of {10 steps UP, 8 steps DOWN, 8 steps LEFT, 7 steps RIGHT} would give the following margin values:

• 50 mV margin UP
• 40 mV margin DOWN
• 0.16 UI margin LEFT
• 0.14 UI margin RIGHT

The lane margin values above sum to a total margin on this PCIe lane of (40 + 50) = 90 mV eye height and (0.16 + 0.14) = 0.3 UI eye width (where the conversion of UI to ps is data rate dependent).

In general, lane margining at the receiver allows system designers to monitor eye height and eye width at either a root complex or PCIe endpoint, which provides insight into the signal quality of the eye at a PCIe receiver. Eye Scan gives system designers a way to additionally monitor eye quality at the Texas Instruments PCIe redriver transmitter, which can help provide insight into vertical eye quality and to find a range of well-performing redriver equalization (EQ) settings for a PCIe link.