There are several options for loopback tests that test and verify various functional blocks within the PHY. Enabling loopback mode allows you to inspect the connections between the MAC and the PHY using xMII/PCS/Digital/AFE loopbacks as well as between the PHY and the MDI using reverse loopback.

The analog loopback is recommended for checking the full data path between the MAC and PHY, while reverse loopback is used with a link partner to verify the data path between the PHY and the MDI(Link Partner).

The device also incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. BIST can be performed using various loopback modes to isolate any issues to specific parts of the data path by generating packetized data with variable content. Scripts are provided to enable data generator/checker as well as the various loopback modes.

Transmitting and Receiving Packets with the MAC:

If generating and checking packets with the MAC is possible, and the PHY has a working link partner with reverse loopback capability, verify the full data path as follows:

1. Power and connect the PHY to the MAC and a working link partner.
2. Enable reverse loopback on the link partner.
3. Transmit test packets from the MAC to the PHY.
4. Verify the MAC receives the same test packets.

If the MAC receives the same test packets transmitted without issue, the full data path through MAC → PHY → Link Partner (MDI) is valid. If this test does not pass, perform analog loopback to isolate the issue along the data path (disconnect cable side connections before running analog loopback):

1. Power and connect the PHY to the MAC.
2. Enable analog loopback on the PHY (write Register 0x0016 = 0x0108).
3. Transmit test packets from the MAC to the PHY.
4. Verify the MAC receives the same test packets.

If the MAC receives the same test packets, the data path through MAC → PHY is valid, and the issue has been isolated to the MDI data path. If this test does not pass, the issue can be on the MAC interface. To check the MAC interface, see Debug the MAC Interface.

Below are example sequence of register reads and writes to perform Analog Loopback:

// Analog Loopback

begin

001F 8000 //Hard Reset
0000 2100 //Disables Auto-Neg, Selects 100 Mbps
0016 0108 //Select Analog Loopback
030B 3380 //This helps PRBS LOCK

0016 3108 //Enables PRBS Checker Config & Packet Generation Enable
 //After you write '3108' the register should Read 3b04. (Bit 11 & 9 go high)
001B 807D //Lock Error Counter's Value
001B

//after running this test check register 0010 bit 0 should be 1 
end

Transmitting and Receiving Packets with BIST:

If generating and checking packets with the MAC is not possible, use an external packet generator or internal PRBS packet generation and check functionalities to verify the data path. Perform reverse loopback with PRBS and a working link partner as follows:

1. Power and connect the PHY to a link partner.
2. Enable PRBS packet generation on the PHY (write 0x16 to 5000).
3. Enable reverse loopback on the link partner
4. Wait at least one second, then check PRBS lock status on the PHY (read register 0x17[11:10]).

If register 0x17[11] is high, the data path through PHY → MDI is valid. If this test does not pass, the issue could be on the PHY's internal data path or the MDI. To verify the internal data path, perform PRBS with analog loopback using the following script. If the internal data path is valid, then the issue is isolated to the MDI (assuming the link partner is working).

Below are example sequences of register reads and writes to perform BIST when using two DP83822 PHY's:

// Reverse Loopback on PHY

begin

001F 8000 //Hard Reset
0000 2100 //Disables Auto-Neg, Selects 100 Mbps
0016 5000 //Enables PRBS packet generation
0017 // check PRBS lock status

end

// Reverse Loopback on Link Partner

begin

001F 8000 //Hard Reset
0000 2100 //Disables Auto-Neg, Selects 100 Mbps
0016 0110 //Select Reverse Loopback

end