SNLA466A August   2024  – October 2024 DP83822I , DP83826E , DP83826I , DP83867E , DP83867IR , DP83869HM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Abbreviation
  5. 2Introduction
  6. 3EMC Emission
    1. 3.1 Radiated Emission
      1. 3.1.1 Test Setup for Radiated Emission Test
      2. 3.1.2 Main Radiated Emission Sources
    2. 3.2 Conducted Emission
      1. 3.2.1 Test Setup for Conducted Emission Test
      2. 3.2.2 Main Conducted Emission Sources
    3. 3.3 Debug Procedure on EMC Emission
      1. 3.3.1 General Debug Procedure
      2. 3.3.2 RE Specific Debug
      3. 3.3.3 CE Specific Debug
  7. 4EMC Immunity Test
    1. 4.1 EMI Passing Criteria
    2. 4.2 Common EMI Knowledge
    3. 4.3 IEC61000 4-2 ESD
      1. 4.3.1 ESD Test Setup
      2. 4.3.2 Possible Root Cause of Failure
      3. 4.3.3 Debug Procedure
        1. 4.3.3.1 Follow the Test Setup
        2. 4.3.3.2 Remove External Factors on Cable or Link Partner
        3. 4.3.3.3 Areas to Explore to Improve ESD Performance
          1. 4.3.3.3.1 Air or Capacitive Coupling Discharge ESD Recommendations
          2. 4.3.3.3.2 Direct Contact Discharge ESD Recommendation
        4. 4.3.3.4 Schematic and Layout Recommendations
    4. 4.4 IEC 61000 4-3 RI
      1. 4.4.1 RI Test Setup
      2. 4.4.2 Possible Root Cause of Failure
      3. 4.4.3 Debug Procedure
        1. 4.4.3.1 Follow RI Test Setup
        2. 4.4.3.2 Remove External Factor on Cable or Link Partner
        3. 4.4.3.3 Found out Main Emission Area
        4. 4.4.3.4 Schematic and Layout Recommendation
    5. 4.5 IEC 61000 4-4 EFT
      1. 4.5.1 EFT Test Setup
      2. 4.5.2 Possible Root Cause of Failure
      3. 4.5.3 Debug Procedure
        1. 4.5.3.1 Follow EFT Test Setup
        2. 4.5.3.2 Remove External Factor on Cable or Link Parnter
        3. 4.5.3.3 Areas to Explore to Improve EFT Performance
        4. 4.5.3.4 Schematic and Layout Recommendation
    6. 4.6 IEC 61000 4-5 Surge
      1. 4.6.1 Surge Test Setup
      2. 4.6.2 Possible Root Cause of Failure
      3. 4.6.3 Debug Procedure
        1. 4.6.3.1 Follow Surge Test Setup
        2. 4.6.3.2 Remove External Factor on Cable or Link Partner
        3. 4.6.3.3 Area to Explore to Improve Surge Performance
        4. 4.6.3.4 Schematic and Layout Recommendation
    7. 4.7 IEC 61000 4-6 CI
      1. 4.7.1 CI Test Setup
      2. 4.7.2 Possible Root Cause of Failure
      3. 4.7.3 Debug Procedure
        1. 4.7.3.1 Follow CI Test Setup
        2. 4.7.3.2 Remove External Factors on Cable or Link Partner
        3. 4.7.3.3 Areas to Explore to Improve CI Performance
        4. 4.7.3.4 Schematic and Layout Recommendation
  8. 5Schematic and Layout Recommendation for All EMC, EMI Tests
    1. 5.1 Schematic Recommendation
    2. 5.2 Layout Recommendation
  9. 6Summary
  10. 7References
  11. 8Revision History

Schematic Recommendation

Relevant Test Recommendation Explanation
General EMC Immunity and Emission test No test point is recommended on the MDI lines
  • Prevents any noise captured to or from the surroundings
General EMI test No shorted center taps (voltage mode driver only)
  • Shorted center taps can increase the common mode noise on the MDI lines
  • Shorted center taps can increase cross talk between TX and RX
  • Shorted center taps can also affect the bias voltage point on TX
  • Prevents current leakage between transmitter and reciever during Auto-MDIX
General EMI test Galvanic isolation (transformer) is highly recommended instead of capacitive coupling
  • Greatly reduces the common mode noise going into the PHY or system
  • Improves isolation between the connector and PHY
General EMI Termination on MDI lines need to be 1% tolerance for current mode driver
  • More precise terminations can reduce the impedance mismatch and prevent reflections on the MDI lines
General EMI Ferrite beads on the pull up resistor on MDI lines for current mode driver PHY (DP83822 and DP83848)
  • Ferrite beads on the pull up resistor on MDI lines (current mode driver). Filters out noise from the power supply, improving CE tests and other power supply EMI test.
ESD and EFT

Ground isolation between system ground and connector ground using R//C connection

  • Prevents direct high voltage noise injection on the system ground
  • R//C is recommended to prevent connector ground charging up significantly after multiple ESD/EFT strikes.
    • Capacitor provides limited noise flow to the system ground while preventing sudden high voltage jumps on the system ground
    • Resistor is used to discharge the capacitor after clamping due to multiple ESD/EFT events
Make sure the R//C connection is not near any signal or clock traces
ESD and EFT Add additional Common Mode Choke (CMC) near the PHY side

In typical applications, the CMC is placed between the transformer and RJ45 connector. This filters out most of the common mode noise coming from the cable.

  • Adding an external CMC near the PHY side can prevent any further noise picked up from the ground to MDI lines, or noise picked up from the surroundings to the MDI lines between the PHY and transformer area
ESD and EFT Replace existing center tap with 0.1uF // 1uF on the PHY's side transformer center tap
  • Provides a path for common mode noise to discharge at different frequencies
Power surge and RI Add Ferrite beads on VDDA and VDDIO
  • Prevents any noise from VDDIO from having a direct effect on VDDA
  • Buck converter can generate high frequency due to the harmonics of the switching frequency
  • Input decoupling capacitors are able to filter out the most of the frequencies, but not the higher ranges
    • Placing a ferrite bead close to the noise source can greatly help with this high frequency noise
Power surge Add Pi-filter on the power side
  • Pi filter on the system can eliminate the noise due to the power cable in for lower frequencies
    • Take into account the resonance of the Pi filter. Capacitors with significant ESR is a good choice to reduce the resonance
Power Surge Common mode choke on the power side
  • Common mode choke on the power supply is also recommended to prevent any common mode noise