SNLA466A August   2024  – October 2024 DP83822I , DP83826E , DP83826I , DP83867E , DP83867IR , DP83869HM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Abbreviation
  5. 2Introduction
  6. 3EMC Emission
    1. 3.1 Radiated Emission
      1. 3.1.1 Test Setup for Radiated Emission Test
      2. 3.1.2 Main Radiated Emission Sources
    2. 3.2 Conducted Emission
      1. 3.2.1 Test Setup for Conducted Emission Test
      2. 3.2.2 Main Conducted Emission Sources
    3. 3.3 Debug Procedure on EMC Emission
      1. 3.3.1 General Debug Procedure
      2. 3.3.2 RE Specific Debug
      3. 3.3.3 CE Specific Debug
  7. 4EMC Immunity Test
    1. 4.1 EMI Passing Criteria
    2. 4.2 Common EMI Knowledge
    3. 4.3 IEC61000 4-2 ESD
      1. 4.3.1 ESD Test Setup
      2. 4.3.2 Possible Root Cause of Failure
      3. 4.3.3 Debug Procedure
        1. 4.3.3.1 Follow the Test Setup
        2. 4.3.3.2 Remove External Factors on Cable or Link Partner
        3. 4.3.3.3 Areas to Explore to Improve ESD Performance
          1. 4.3.3.3.1 Air or Capacitive Coupling Discharge ESD Recommendations
          2. 4.3.3.3.2 Direct Contact Discharge ESD Recommendation
        4. 4.3.3.4 Schematic and Layout Recommendations
    4. 4.4 IEC 61000 4-3 RI
      1. 4.4.1 RI Test Setup
      2. 4.4.2 Possible Root Cause of Failure
      3. 4.4.3 Debug Procedure
        1. 4.4.3.1 Follow RI Test Setup
        2. 4.4.3.2 Remove External Factor on Cable or Link Partner
        3. 4.4.3.3 Found out Main Emission Area
        4. 4.4.3.4 Schematic and Layout Recommendation
    5. 4.5 IEC 61000 4-4 EFT
      1. 4.5.1 EFT Test Setup
      2. 4.5.2 Possible Root Cause of Failure
      3. 4.5.3 Debug Procedure
        1. 4.5.3.1 Follow EFT Test Setup
        2. 4.5.3.2 Remove External Factor on Cable or Link Parnter
        3. 4.5.3.3 Areas to Explore to Improve EFT Performance
        4. 4.5.3.4 Schematic and Layout Recommendation
    6. 4.6 IEC 61000 4-5 Surge
      1. 4.6.1 Surge Test Setup
      2. 4.6.2 Possible Root Cause of Failure
      3. 4.6.3 Debug Procedure
        1. 4.6.3.1 Follow Surge Test Setup
        2. 4.6.3.2 Remove External Factor on Cable or Link Partner
        3. 4.6.3.3 Area to Explore to Improve Surge Performance
        4. 4.6.3.4 Schematic and Layout Recommendation
    7. 4.7 IEC 61000 4-6 CI
      1. 4.7.1 CI Test Setup
      2. 4.7.2 Possible Root Cause of Failure
      3. 4.7.3 Debug Procedure
        1. 4.7.3.1 Follow CI Test Setup
        2. 4.7.3.2 Remove External Factors on Cable or Link Partner
        3. 4.7.3.3 Areas to Explore to Improve CI Performance
        4. 4.7.3.4 Schematic and Layout Recommendation
  8. 5Schematic and Layout Recommendation for All EMC, EMI Tests
    1. 5.1 Schematic Recommendation
    2. 5.2 Layout Recommendation
  9. 6Summary
  10. 7References
  11. 8Revision History

Found out Main Emission Area

After performing the above tests and failures are still observed, the issue is most likely on the DUT boards. Further action is to use copper tape to cover or shield the area on the boards that is suspected to be most sensitive. Copper tape needs to be strongly connected to earth ground so that the copper tape can absorb most of the emission noise. If the copper tape is not connected to earth ground properly, the copper take can act as an antenna source, amplifying the signals from the covered area:

  • Shield around MAC pins to minimize the exposure of MAC pins to the radiation source if the MAC is not used for testing
  • Shield area around the MDI lines with earth ground. If covering MDI lines helps with RI testing performance, here are some recommendations for further improvement on MDI lines:
    • Minimize vias around MDI lines
    • Minimize components or exposed pads on the MDI lines
    • If possible, bury the MDI traces during RI tests
    • Symmetry on the MDI lines
  • Shield area around the Rbias pin and traces. If covering Rbias pin and traces helps with RI performance, please follow the recommendations below:
    • Rbias is the reference current to drive the PHY internally. Having the optimal layout around Rbias area can help with RI testing performance
    • Bury Rbias trace in inner layer
    • Minimize vias around Rbias
    • Minimize Rbias component size
  • Shield the oscillator or clock signal to see if that helps with RI performance
  • Shield around the power lines to see if that helps with RI performance