SNLA466 Application note

SNLA466A August 2024 – October 2024 DP83822I , DP83826E , DP83826I , DP83867E , DP83867IR , DP83869HM

5.2 Layout Recommendation

1. MDI lines recommendation:

Relevant Test	Recommendation	Explanation
Both PHY side and RJ45 connector side MDI recommendations
General EMI	Symmetry and same pad footprints and position of differential pairs on MDI lines	Reduces mode conversion effect on EMI testing
General EMI	Impedance match of MDI lines	Reduces reflections on the signal lines
General EMI	Continuous ground layer under MDI lines	Continuous ground layer under MDI lines can provide constant impedance matching on MDI lines Impedance discontinuities cause unwanted signal reflections. Signal crossing over a plane split can cause unpredictable return path currents and can likely impact signal quality as well, potentially creating EMI problems.
General EMI	Length Matching	When matching the intra pair length of high-speed signals. The serpentine routing need to be as close as possible to the mismatched ends Reduces the effect of differential mode noise
General EMI	Minimize MDI trace bending	Limiting the MDI trace bending can minimize the effect of cross talk between different sections of the MDI trace. Reduces the noise introduced on the MDI traces
General EMC	No sharp turns on MDI lines	Reduces the emission point with round turns on MDI line (ESD Protection Layout Guide

ESD and EFT	Avoid polygon pours (keep out region) under/near transformer	Prevents noise injected directly to the transformer through the ground polygon pour during EMI events. Polygon pours under the transformer can decrease the transformer's isolation functionality
ESD and EFT	Discrete magnetic and RJ45 connector is recommended	Integrated RJ45 magnetics have an isolation network inside the RJ45 shield. If any noise is injected onto the RJ45 shield, the transformer's performance can degrade significantly. Some of the noise can bypass the isolation network and directly couple to system ground or the MDI lines. Discrete magnetics can minimize the injection noise on the RJ45 shield and have a direct impact on the digital ground or MDI lines, improving the transformer performance
EMC, ESD and possibly RI	Short length on MDI lines	Shorter MDI lines can shorten the exposed path to the surroundings and reduce the radiated coupling noise
ESD and possibly RI	Minimum vias on MDI lines	Reduce number of vias on MDI lines to reduce the noise picked up from the surroundings, as well as emission to the surroundings Vias on MDI lines can result in impedance discontinuities, causing unwanted signal reflections
General EMC Emission and Immunity	Minimize exposed area on MDI lines	Minimize exposed area on MDI lines to reduce the emissions and radiative noise picked up on the MDI lines
General EMC Emission	Prevent any signal wire crossing with MDI lines without any ground plane separation	Signal wire crossing on consecutive layers can result in larger emissions
RJ45 connector layout recommendation
ESD and EFT	Minimize vias around the MDI lines on the connector ground	Vias around the MDI lines can create a better path for ESD/EFT noise current to flow between MDI lines, increasing the chance of interference with MDI signal lines
ESD and EFT	No ground polygon pour of connector ground around the MDI lines on the same layer	Reduces the ground bounce interference from the connector ground to the MDI lines during ESD/EFT events
ESD and EFT	Clean ground layer under MDI lines (No vias and other power or signal lines)	Better impedance matching Reduces the effect of ground bounce to the MDI lines
General EMI	No power plane and non-MDI trace under RJ45 connector	Prevents any power or other signal trace disturbance during EMI testing Isolates other external noise injected into the MDI lines
ESD and EFT	R//C Ground isolation or other earth ground path circuitry need to be on the opposite layer as the MDI lines	Makes sure most of the EMI noise can flow on the opposite side of the MDI lines and minimize ground noise interference to the MDI lines.
ESD and EFT	Large component size with R//C ground isolation network	Supports large current to prevent any damage during EMI event
ESD and EFT	No vias and ground polygon pours around the bob smith termination	Minimizes the noise interference going into bob smith termination and affecting the signal during EMI testing
ESD	R//C ground connection placed near the power supply	Allowing some EMI noise to flow between connector ground to power ground, routing away from any sensitive circuits Minimizes the noise path to the PHY or other ICs
ESD and EFT	RJ45 module with LEDs are not recommended for better EMI performance	Prevents EMI noise source flowing through the LED lines directly into the PHYs

PHY side MDI recommendation
General EMI	Single differential pair need to be routed as close as possible	Reduces the mode conversion Reduces the chance of picking up sources of differential noise Crosstalk between differential pairs isn't a significant concern Smallest trace spacing is normally selected (5 to 6 mils)
General EMI	Keep some distance between differential pairs	Prevents cross talk between the differential pairs Reduces the common mode noise interference between differential pairs
General EMI	Keep the differential pair on the same reference ground	Reduces the mode conversion due to ground bounced during EMI testing Better impedance matching between differential pairs

2. General Layout recommendation around the PHY:

Relevant Test	Recommendation	Explanation
General EMC Emission	Prevent any signal wires, clock, and power signals crossing without any ground plane separation	Prevents cross talk between the signal lines and reduces EMC emission
General EMC Emission and Immunity	No signal lines next to each other	Prevents cross talk between the signal lines and reduces EMC emission
General EMC Emission	No sharp turns of clock and signal traces	Prevents EMC emission
RI and indirect ESD	Short or buried traces between Rbias pin and resistor	Rbias pin is the internal current reference for the PHY. Short Rbias traces can reduce the radiated noise picked upfrom the surroundings Possible bury the Rbias trace to inner layer if there are layout constraints that can also reduce noise picked up from the surroundings
RI and indirect ESD	Minimize component size of Rbias resistor	Minimize components size of Rbias resistor to reduce the noise picked up by the Rbias resistor

3. Crystal Layout recommendation

Relevant Test	Recommendation	Explanation
ESD and EFT	Keep all crystal components on the same layer	Makes sure crystal components are referenced to the same ground, reducing the ground bounce effect
General EMI and EMC	Isolate crystal and crystal lines with other signal lines	Prevents clock signal disturbance by other signal line
Power surge, ESD and EFT	Isolate crystal ground from MDI and power ground (Ground island)	The ground connection for the load capacitors need to be short and separated from the power line Prevent any effect EMI test effect directly into the clock from either power or MDI lines EMC testing Keeps the noise away from the system ground Verify there are ground vias connected to the ground on other layer to prevent high frequency ringing due to the floating ground
General EMC	Short crystal traces and length matching on the crystal capacitor	Reduces the radiated emission Improves the clock performance and reduces the ground bounce effect
General EMC	Small footprint on crystal capacitor	C1 and C2 are important to use C0G/NP0 capacitors for proper performance in the system Small footprint on crystal capacitor can reduce the emission

4. Oscillator Layout recommendation

Relevant Test	Recommendation	Explanation
General EMI/EMC	Impedance matching on the oscillator traces Adding 50Ω termination on the oscillator traces	Using an oscillator or a clock buffer as a clock source typically expressed as a single ended signal. The oscillator clock trace is matched with a 50Ω termination Series termination and parallel termination are recommended on the oscillator for impedance matching and to minimize the reflection on the clock signal This can give better clock performance or tolerance for EMI, as well as a smaller emission factor
General EMI/EMC	Verify PHY's voltage level specification matches with the oscillator clock signals	If the clock signal does not meet the PHY's specified voltage level, the PHY can have less tolerance for EMI performance Voltage or capacitor divider can be implemented on the oscillator to reduce oscillator clock signal level to improve EMC emission performance
General EMC	Small capacitor footprint for oscillator	Small footprint (C0G/NP0 is recommended) to reduce emissions

Relevant Test

Recommendation

Explanation

General EMI/EMC

Impedance matching on the oscillator traces Adding 50Ω termination on the oscillator traces

Using an oscillator or a clock buffer as a clock source typically expressed as a single ended signal. The oscillator clock trace is matched with a 50Ω termination

Series termination and parallel termination are recommended on the oscillator for impedance matching and to minimize the reflection on the clock signal
This can give better clock performance or tolerance for EMI, as well as a smaller emission factor

General EMI/EMC

Verify PHY's voltage level specification matches with the oscillator clock signals

If the clock signal does not meet the PHY's specified voltage level, the PHY can have less tolerance for EMI performance

Voltage or capacitor divider can be implemented on the oscillator to reduce oscillator clock signal level to improve EMC emission performance

General EMC

Small capacitor footprint for oscillator

Small footprint (C0G/NP0 is recommended) to reduce emissions

5. Power Layout recommendation

Relevant Test	Recommendation	Explanation
Power Surge or General EMI for current mode driver device	Total decoupling capacitance > load capacitance	The total decoupling capacitance need to be greater than the load capacitance presented to the digital output buffers to prevent noise from being introduced into the supply
Power Surge or General EMI for current mode driver device	Decoupling capacitor size selection (small caps to filter higher frequency noise)	Decoupling caps: Smaller package size is recommend for high frequency caps The physical size makes a difference with smaller footprints having lower series inductance for better high frequency performance. Also, avoid through hole or electrolytic cap footprints for filtering in this case. Capacitor changes over frequency and has parasitics. Typically small capacitance values are designed for filtering high frequency values Small capacitor need to be place closest to the PHY with incremental values
Power Surge or General EMI for current mode driver device	Ground vias near decoupling caps	All decoupling capacitors must be connected directly to a low impedance ground plane (vias to ground plane) Strongly consider connecting the ground of all bypass capacitors with two vias to greatly reduce the inductance of that connection.
Power Surge or General EMI for current mode driver device	Solid ground plane on power supply	Provides a good low impedance return path for the power supply current (especially for high frequency ripple) to go through the decoupling caps.
Power Surge or General EMI for current mode driver device	Wide and short power traces are recommended	Trace connections need to be as wide as possible to lower inductance and reduce the noise and electromagnetic interference
Power Surge or General EMI for current mode driver device	Pi filter need to be placed near the input connector	Pi filter need to be near the input connector to prevent the low frequency noise
Power Surge or General EMI for current mode driver device	Common mode choke on the power supply is recommended	Common mode choke is recommended for isolation between the power supply. If there is a voltage offset between the power supply and system, the common mode choke can prevent or slow the transition in between. Make sure the common mode choke has a cut out ground plane or empty ground plane Typical path for common mode noise in the supply is through decoupling caps from ground bounce to supply or the inverse. Therefore, it is crucial to make sure no ground noise is interfering or coupling with the common mode choke.