SNLA466A August   2024  – October 2024 DP83822I , DP83826E , DP83826I , DP83867E , DP83867IR , DP83869HM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Abbreviation
  5. 2Introduction
  6. 3EMC Emission
    1. 3.1 Radiated Emission
      1. 3.1.1 Test Setup for Radiated Emission Test
      2. 3.1.2 Main Radiated Emission Sources
    2. 3.2 Conducted Emission
      1. 3.2.1 Test Setup for Conducted Emission Test
      2. 3.2.2 Main Conducted Emission Sources
    3. 3.3 Debug Procedure on EMC Emission
      1. 3.3.1 General Debug Procedure
      2. 3.3.2 RE Specific Debug
      3. 3.3.3 CE Specific Debug
  7. 4EMC Immunity Test
    1. 4.1 EMI Passing Criteria
    2. 4.2 Common EMI Knowledge
    3. 4.3 IEC61000 4-2 ESD
      1. 4.3.1 ESD Test Setup
      2. 4.3.2 Possible Root Cause of Failure
      3. 4.3.3 Debug Procedure
        1. 4.3.3.1 Follow the Test Setup
        2. 4.3.3.2 Remove External Factors on Cable or Link Partner
        3. 4.3.3.3 Areas to Explore to Improve ESD Performance
          1. 4.3.3.3.1 Air or Capacitive Coupling Discharge ESD Recommendations
          2. 4.3.3.3.2 Direct Contact Discharge ESD Recommendation
        4. 4.3.3.4 Schematic and Layout Recommendations
    4. 4.4 IEC 61000 4-3 RI
      1. 4.4.1 RI Test Setup
      2. 4.4.2 Possible Root Cause of Failure
      3. 4.4.3 Debug Procedure
        1. 4.4.3.1 Follow RI Test Setup
        2. 4.4.3.2 Remove External Factor on Cable or Link Partner
        3. 4.4.3.3 Found out Main Emission Area
        4. 4.4.3.4 Schematic and Layout Recommendation
    5. 4.5 IEC 61000 4-4 EFT
      1. 4.5.1 EFT Test Setup
      2. 4.5.2 Possible Root Cause of Failure
      3. 4.5.3 Debug Procedure
        1. 4.5.3.1 Follow EFT Test Setup
        2. 4.5.3.2 Remove External Factor on Cable or Link Parnter
        3. 4.5.3.3 Areas to Explore to Improve EFT Performance
        4. 4.5.3.4 Schematic and Layout Recommendation
    6. 4.6 IEC 61000 4-5 Surge
      1. 4.6.1 Surge Test Setup
      2. 4.6.2 Possible Root Cause of Failure
      3. 4.6.3 Debug Procedure
        1. 4.6.3.1 Follow Surge Test Setup
        2. 4.6.3.2 Remove External Factor on Cable or Link Partner
        3. 4.6.3.3 Area to Explore to Improve Surge Performance
        4. 4.6.3.4 Schematic and Layout Recommendation
    7. 4.7 IEC 61000 4-6 CI
      1. 4.7.1 CI Test Setup
      2. 4.7.2 Possible Root Cause of Failure
      3. 4.7.3 Debug Procedure
        1. 4.7.3.1 Follow CI Test Setup
        2. 4.7.3.2 Remove External Factors on Cable or Link Partner
        3. 4.7.3.3 Areas to Explore to Improve CI Performance
        4. 4.7.3.4 Schematic and Layout Recommendation
  8. 5Schematic and Layout Recommendation for All EMC, EMI Tests
    1. 5.1 Schematic Recommendation
    2. 5.2 Layout Recommendation
  9. 6Summary
  10. 7References
  11. 8Revision History

4.5 IEC 61000 4-4 EFT

IEC 61000-4-4 is also known as Electrical Fast Transient (EFT) EMC Burst Immunity Test Standard. EFT mainly tests the immunity of electrical equipment when subjected to fast transient/burst electrical signals. In EFT tests, a common mode burst signal from a burst generator is sent to the Ethernet cable through capacitive clamping. This clamping is 1 meter long, directly mounted to earth ground. Unlike ESD testing which has a one second interval between each pulse, EFT testing has a pulse interval in the microsecond range. Therefore, optimizing the design for noise discharge is crucial for EFT testing. Shielded and non-shielded cables play a significant role in EFT performance. Since EFT tests are based on clamping the Ethernet cable using capacitive coupling equipment, the noise normally injects from the equipment and directly couples inside the Ethernet cable. If the customer is using a shielded cable, most of the noise can flow to the connector ground instead of the signal lines, since the shield is normally connected to earth ground. This can significantly improve EFT performance. Therefore, shielded cables are highly recommended for EMC applications.

In the IEC 61000 4-4 standard, EFT tests also define power port testing. In addition to power EMC tests relying on not only Ethernet PHY, but also rely on system-level power ICs (Buck converters, LDOs, power switches, etc). Therefore, this section can focus on how to debug EMC failures in Ethernet applications on signal ports. There are layout recommendation for the power ports around the PHY side, but the below sections focuses on signal port EFT testing.

EFT test level:

  • Test level 1: ±0.5kV
  • Test level 2: ± 1kV
  • Test level 3: ±2kV
  • Test level 4: ±4kV
Note:

Class A, Class B, and Class C depend on customer’s requirement

EFT test waveform:

Two frequency burst signals need to be tested for IEC61000 4-4 EFT:

  • 5kHz burst signals have a periodic of 200us for each pulse and total 15ms for the whole burst duration.
  • 100kHz burst signal have a period of 10us for each pulse and total 0.75ms for the whole burst duration.
  • Both 5kHz and 100kHz have a burst period of 300ms.
EFT Test Waveform Figure 4-6 EFT Test Waveform
Note:

IEC61000 4-6 EFT standard only require one passing frequency (5kHz or 100kHz). However, most of the industrial application currently require both 5kHz and 100kHz to consider as passing criteria.