SNLS430C October   2012  – August 2014 DS125BR111

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics — Serial Management Bus Interface
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Functional Datapath Blocks
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Mode
      3. 8.4.3 Signal Conditioning Settings
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 Transfer Of Data Via The SMBus
      2. 8.6.2 SMBus Transactions
      3. 8.6.3 Writing a Register
      4. 8.6.4 Reading a Register
      5. 8.6.5 SMBus Register Information
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Signal Integrity
      2. 9.1.2 RX-Detect in SAS/SATA Applications
      3. 9.1.3 PCIe Applications
        1. 9.1.3.1 RXDET When Using SMBus Modes
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

10 Power Supply Recommendations

Two approaches are recommended to ensure that the DS125BR111 is provided with an adequate power supply. First, the supply (VDD) and ground (GND) Pins should be connected to power planes routed on adjacent layers of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.1 μF bypass capacitor should be connected to each VDD Pin such that the capacitor is placed as close as possible to the DS125BR111. Smaller body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in the range of 1 μF to 10 μF should be incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic.

The DS125BR111 has an optional internal voltage regulator to provide the 2.5 V supply to the device. In 3.3 V mode operation, the VIN Pin = 3.3 V is used to supply power to the device. The internal regulator will provide the 2.5 V to the VDD Pins of the device and a 0.1 µF cap is needed at each of the 2 VDD Pins for power supply de-coupling (total capacitance should equal 0.2 µF). The VDD_SEL Pin must be tied to GND to enable the internal regulator. In 2.5 V mode operation, the VIN Pin should be left open and 2.5 V supply must be applied to the 2 VDD Pins to power the device. The VDD_SEL Pin must be left open (no connect) to disable the internal regulator.

111power.gifFigure 11. 3.3 V or 2.5 V Supply Connection Diagram