SNLS552E September   2017  – April 2024 DS90UB953-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Recommended Timing for the Serial Control Bus
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 CSI-2 Receiver
        1. 6.3.1.1 CSI-2 Receiver Operating Modes
        2. 6.3.1.2 CSI-2 Receiver High-Speed Mode
        3. 6.3.1.3 CSI-2 Protocol Layer
        4. 6.3.1.4 CSI-2 Short Packet
        5. 6.3.1.5 CSI-2 Long Packet
        6. 6.3.1.6 CSI-2 Errors and Detection
          1. 6.3.1.6.1 CSI-2 ECC Detection and Correction
          2. 6.3.1.6.2 CSI-2 Check Sum Detection
          3. 6.3.1.6.3 D-PHY Error Detection
          4. 6.3.1.6.4 CSI-2 Receiver Status
      2. 6.3.2 FPD-Link III Forward Channel Transmitter
        1. 6.3.2.1 Frame Format
      3. 6.3.3 FPD-Link III Back Channel Receiver
      4. 6.3.4 Serializer Status and Monitoring
        1. 6.3.4.1 Forward Channel Diagnostics
        2. 6.3.4.2 Back Channel Diagnostics
        3. 6.3.4.3 Voltage and Temperature Sensing
          1. 6.3.4.3.1 Programming Example
        4. 6.3.4.4 Built-In Self Test
      5. 6.3.5 FrameSync Operation
        1. 6.3.5.1 External FrameSync
        2. 6.3.5.2 Internally Generated FrameSync
      6. 6.3.6 GPIO Support
        1. 6.3.6.1 GPIO Status
        2. 6.3.6.2 GPIO Input Control
        3. 6.3.6.3 GPIO Output Control
        4. 6.3.6.4 Forward Channel GPIO
        5. 6.3.6.5 Back Channel GPIO
    4. 6.4 Device Functional Modes
      1. 6.4.1 Clocking Modes
        1. 6.4.1.1 Synchronous Mode
        2. 6.4.1.2 Non-Synchronous Clock Mode
        3. 6.4.1.3 Non-Synchronous Internal Mode
        4. 6.4.1.4 DVP Backwards Compatibility Mode
        5. 6.4.1.5 Configuring CLK_OUT
      2. 6.4.2 MODE
    5. 6.5 Programming
      1. 6.5.1 I2C Interface Configuration
        1. 6.5.1.1 CLK_OUT/IDX
          1. 6.5.1.1.1 IDX
      2. 6.5.2 I2C Interface Operation
      3. 6.5.3 I2C Timing
    6. 6.6 Pattern Generation
      1. 6.6.1 Reference Color Bar Pattern
      2. 6.6.2 Fixed Color Patterns
      3. 6.6.3 Packet Generator Programming
        1. 6.6.3.1 Determining Color Bar Size
      4. 6.6.4 Code Example for Pattern Generator
    7. 6.7 Register Maps
      1. 6.7.1 Main Registers
        1. 6.7.1.1  I2C Device ID Register
        2. 6.7.1.2  Reset
        3. 6.7.1.3  General Configuration
        4. 6.7.1.4  Forward Channel Mode Selection
        5. 6.7.1.5  BC_MODE_SELECT
        6. 6.7.1.6  PLL Clock Control
        7. 6.7.1.7  Clock Output Control 0
        8. 6.7.1.8  Clock Output Control 1
        9. 6.7.1.9  Back Channel Watchdog Control
        10. 6.7.1.10 I2C Control 1
        11. 6.7.1.11 I2C Control 2
        12. 6.7.1.12 SCL High Time
        13. 6.7.1.13 SCL Low Time
        14. 6.7.1.14 Local GPIO DATA
        15. 6.7.1.15 GPIO Input Control
        16. 6.7.1.16 DVP_CFG
        17. 6.7.1.17 DVP_DT
        18. 6.7.1.18 Force BIST Error
        19. 6.7.1.19 Remote BIST Control
        20. 6.7.1.20 Sensor Voltage Gain
        21. 6.7.1.21 Sensor Control 0
        22. 6.7.1.22 Sensor Control 1
        23. 6.7.1.23 Voltage Sensor 0 Thresholds
        24. 6.7.1.24 Voltage Sensor 1 Thresholds
        25. 6.7.1.25 Temperature Sensor Thresholds
        26. 6.7.1.26 CSI-2 Alarm Enable
        27. 6.7.1.27 Alarm Sense Enable
        28. 6.7.1.28 Back Channel Alarm Enable
        29. 6.7.1.29 CSI-2 Polarity Select
        30. 6.7.1.30 CSI-2 LP Mode Polarity
        31. 6.7.1.31 CSI-2 High-Speed RX Enable
        32. 6.7.1.32 CSI-2 Low Power Enable
        33. 6.7.1.33 CSI-2 Termination Enable
        34. 6.7.1.34 CSI-2 Packet Header Control
        35. 6.7.1.35 Back Channel Configuration
        36. 6.7.1.36 Datapath Control 1
        37. 6.7.1.37 Remote Partner Capabilities 1
        38. 6.7.1.38 Partner Deserializer ID
        39. 6.7.1.39 Target 0 ID
        40. 6.7.1.40 Target 1 ID
        41. 6.7.1.41 Target 2 ID
        42. 6.7.1.42 Target 3 ID
        43. 6.7.1.43 Target 4 ID
        44. 6.7.1.44 Target 5 ID
        45. 6.7.1.45 Target 6 ID
        46. 6.7.1.46 Target 7 ID
        47. 6.7.1.47 Target 0 Alias
        48. 6.7.1.48 Target 1 Alias
        49. 6.7.1.49 Target 2 Alias
        50. 6.7.1.50 Target 3 Alias
        51. 6.7.1.51 Target 4 Alias
        52. 6.7.1.52 Target 5 Alias
        53. 6.7.1.53 Target 6 Alias
        54. 6.7.1.54 Target 7 Alias
        55. 6.7.1.55 Back Channel Control
        56. 6.7.1.56 Revision ID
        57. 6.7.1.57 Device Status
        58. 6.7.1.58 General Status
        59. 6.7.1.59 GPIO Pin Status
        60. 6.7.1.60 BIST Error Count
        61. 6.7.1.61 CRC Error Count 1
        62. 6.7.1.62 CRC Error Count 2
        63. 6.7.1.63 Sensor Status
        64. 6.7.1.64 Sensor V0
        65. 6.7.1.65 Sensor V1
        66. 6.7.1.66 Sensor T
        67. 6.7.1.67 CSI-2 Error Count
        68. 6.7.1.68 CSI-2 Error Status
        69. 6.7.1.69 CSI-2 Errors Data Lanes 0 and 1
        70. 6.7.1.70 CSI-2 Errors Data Lanes 2 and 3
        71. 6.7.1.71 CSI-2 Errors Clock Lane
        72. 6.7.1.72 CSI-2 Packet Header Data
        73. 6.7.1.73 Packet Header Word Count 0
        74. 6.7.1.74 Packet Header Word Count 1
        75. 6.7.1.75 CSI-2 ECC
        76. 6.7.1.76 IND_ACC_CTL
        77. 6.7.1.77 IND_ACC_ADDR
        78. 6.7.1.78 IND_ACC_DATA
        79. 6.7.1.79 FPD3_TX_ID0
        80. 6.7.1.80 FPD3_TX_ID1
        81. 6.7.1.81 FPD3_TX_ID2
        82. 6.7.1.82 FPD3_TX_ID3
        83. 6.7.1.83 FPD3_TX_ID4
        84. 6.7.1.84 FPD3_TX_ID5
      2. 6.7.2 Indirect Access Registers
        1. 6.7.2.1 PATGEN Registers
        2. 6.7.2.2 Analog Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power-over-Coax
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 CSI-2 Interface
        2. 7.2.2.2 FPD-Link III Input / Output
        3. 7.2.2.3 Internal Regulator Bypassing
        4. 7.2.2.4 Loop Filter Decoupling
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power-Up Sequencing
        1. 7.3.1.1 System Initialization
          1. 7.3.1.1.1 Code Example for Temperature Ramp Initialization
      2. 7.3.2 Power Down (PDB)
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 CSI-2 Guidelines
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

9 Revision History

Changes from Revision D (March 2023) to Revision E (April 2024)

  • Added reference to "I2C Bus Pullup Resistor Calculation" Application Note to I2C_SCL and I2C_SDA pin description Go
  • Updated specifications for maximum operating free air temperature and ending temperature when ambient temperature is decreasing from start upGo
  • Added table for deserializer SENSOR_STS_x bit description Go
  • Denoted CSI-2 rate must meet the limitations shown in Clocking Modes tableGo
  • Clarified PGEN_LINE_PD is calculated based on frame rate, total lines per frame, and forward channel rateGo
  • Published main page register 0x1E ALARM_BC_EN[6:2]Go
  • Published Analog registers 0x4B and 0x4CGo
  • Updated Typical PoC Network example to include reference to Design Parameters Table Go
  • Changed Typical Applications diagram for Coax and STP to reference Rpu Go
  • Added information describing serializer system initialization for continuous PLL lock Go
  • Added initialization sequence example for continuous PLL lock during serializer temperature ramp Go

Changes from Revision C (October 2020) to Revision D (March 2023)

  • Typical power consumption bullet on front page updated to match electrical characteristics tableGo
  • IDD_TOTAL typical value changed to 160 mAGo
  • Changed I2C terminology to "Controller" and "Target"Go
  • Removed extra arrow from DPHY Receiver to Clock Gen blocks in Functional Block DiagramGo
  • Added description for non-continuous clock lane modeGo
  • Added description for deserializer SENSOR_STS registersGo
  • Updated script example for voltage monitoringGo
  • Updated description for reading GPIO status when set as output and added GPIO Configuration tableGo
  • Added information for enabling Forward Channel GPIO using FC_GPIO_ENGo
  • Updated GPIO Output Control section description for enabling register 0x0EGo
  • Added typical latency to Forward Channel GPIO tableGo
  • Updated Clocking Mode table with additional modes, frequency clarifications, and CSI-2 bandwidth clarificationsGo
  • Corrected effect of setting M value in register 0x06 Go
  • Updated description to refer to "DVP_DT_MATCH_EN" in register 0x11. Go
  • Changed 0x17[7:4] default value from 0x0 to 0x3Go
  • Added max and min readings to Voltage Sensor Thresholds description in Register 0x19 Go
  • Updated SENSOR_V1_THRESH description to match SENSOR_V0_THRESH in register 0x1AGo
  • Changed "GPIO0 Sensor" to "Internal Temperature Sensor" in register 0x57Go
  • Changed "FPD3_RX_ID" to "FPD3_TX_ID" in registers 0xF0-0xF5Go
  • Changed PoC network impedance recommendation from 2kΩ to 1kΩGo
  • Updated PoC descriptionGo
  • Removed IL and RL values from Suggested Characteristics for Single-Ended PCB Traces With Attached PoC Networks TableGo
  • Changed FB1-FB3 requirement to DCR < 500mΩ.Go
  • Added note for setting watchdog timer for system initializationGo
  • Corrected PDB capacitor from 1μF to 10μFGo

Changes from Revision B (September 2018) to Revision C (October 2020)

  • Added feature bullet Functional Safety Capable.Go

Changes from Revision A (February 2018) to Revision B (September 2018)

  • Updated GPIO pin descriptions. Go
  • Replace CLK_IN with clock throughout document. Go
  • Changed Supply voltage from 2.5V to 2.16VGo
  • Added note for supply noise frequency rangeGo
  • Added internal reference frequency in EC tableGo
  • Added Internal AON Clock to Block Diagram.Go
  • Changed mode to modes. Go
  • Changed 130ns to 225ns.Go
  • Changed latency to 1.5us and jitter to 0.7us. Go
  • Changed CLK_IN Mode to Modes. Go
  • Added DVP Mode Go
  • Changed table formatting. Go
  • Changed REFLCK to Back Channel Go
  • Added Frequency for Synchronous Mode Go
  • Changed naming convention from "asynchronous CLK_IN" to "Non-Synchronous external CLK_IN" mode column dor CLKIN_DIV = 2Go
  • Added Non-Synchronous Internal Clock Mode Go
  • Changed the value from 24.2 - 25.5MHz to 48.4 - 51MHz Go
  • Changed the value from 25 - 52MHz to 24.2 to 25.5MHz Go
  • Added DVP External Clock.Go
  • Added text "Deserializer Mode" to clarify mode RAW10 Go
  • Added text "Deserializer Mode" to clarify mode RAW12 HF Go
  • Added additional information to note. Go
  • Added Added Footnote for Local Reference Source Go
  • Changed CLK_IN to Clock.Go
  • Added Non-Synchronous Internal Clocking Mode section. Go
  • Changed the internal clock 25MHz to 24.2MHz Go
  • Changed forward channel rate to1.936Gbps instead of 2Gbps Go
  • Changed the average CSI-2 throughput value to 3.1Gbps instead of 1.6Gbps Go
  • Added DVP Backwards Compatibility Mode section.Go
  • Changed "asynchronous CLK_IN" to "Non-Synchronous external CLK_IN"Go
  • Added sentence "CLK_OUT functionality is not..."Go
  • Added Non-Synchronous Internal Clock Mode Go
  • Deleted "with accuracy of 25MHz ±10%.Go
  • Changed clock to from 25MHz ±10% to 26.25MHz. Go
  • Changed clock to from 25MHz ±10% to 26.25MHz. Go
  • Updated registers map Go
  • Added information for DVP mode to register 0x04. Go
  • Added "operating with Non-Synchronous internal clock or"Go
  • Added "operating with Non-Synchronous internal clock or"Go
  • Changed the frequency value from 26MHz to range value (24.2MHz to 25.5MHz.) Go
  • Added "set for 2Gbps line rate" Go
  • Changed the frequency value from 52MHz to range value (48.4MHz to 51MHz) Go
  • Added "set for 4Gbps line rate" in register 0x05 Go
  • Updated unit time and clock frequency. Go
  • Added DVP information to register 0x10. Go
  • Added DVP information to register 0x11. Go
  • Deleted the value -25dB and added -20dB in typcial Go
  • Changed –26.4+14.4f to log equation –12+8*log(f) Go
  • Moved Return Loss, S11 MAX values to TYPGo
  • Added Typical connection diagram for STP Go
  • Changed the capacitance value from 33nF to 33nF – 100nF. Go
  • Changed the capacitance value from 15nF to 15nF – 47nF.Go
  • Changed the capacitance value from 33nF to 33nF – 100nF. Go

Changes from Revision * (September 2017) to Revision A (December 2017)

  • Changed RES1 pin description from "Leave OPEN" to "Do not connect" Go
  • Added "Internal 1MΩ pulldown" text to PDB pin descriptionGo
  • Expanded MODE pin description Go
  • Changed "Requires" to "Typically connected to" in the Power and Ground pin descriptions Go
  • Changed "and should not be connected to an external supply" to "Do not connect to an external supply rail" in the Power and Ground pin descriptions Go
  • Changed the CSI_ERR_COUNT (0x5C) text to CSI_ERR_CNT (0x5C)Go
  • Changed DS90UBUB954-Q1 to DS90UB954-Q1Go
  • Changed the GPIO_INPUT_CTL text to GPIO_INPUT_CTRL in the GPIO Input Control and GPIO Output Control sectionsGo
  • Changed CLK_IN lower limit with CLKIN_DIV =1 from 46MHz to 25MHz and CLK_IN lower limit from 92MHz to 50MHz.Go
  • Corrected typo in MODE description saying the number of modes is 3 to the correct value of 2Go
  • Changed I2C START description to "A START occurs when SDA transitions Low while SCLK is High" Go
  • Added sentence and table to clarify reserved registers Go
  • Added registers tables for reserved registers 0x04, 0x0F-0x12, 0x16, 0x1F, 0x25-0x30, 0x34, 0x36, 0x38, 0x4A-0x4F, 0x5B, 0x65-0xAF, and 0xB3-0xEF.Go
  • Changed bit 6 and bit 7 in the MODE_SEL register to RESERVEDGo
  • Changed the SENSE_VO_HI and SENSE_VO_LO registers to SENSE_V0_HI and SENSE_V0_LO to match the title in Table 6-35 Go
  • Changed the SENSE_V0_HI and SENSE_V0_LO bit descriptionsGo
  • Changed the SENSOR_V0_THRESH bit description Go
  • Changed the SENSE_T_HI and SENSE_T_LO bit descriptionsGo
  • Combined the CSI_EN_HSRX register bits 6–0 into one rowGo
  • Combined the CSI_EN_LPRX register bits 6–0 into one rowGo
  • Combined the CSI_EN_RXTERM register bits 7–4 into one rowGo
  • Changed serializer to deserializer in TARGET_ID_ALIAS_x bit descriptions Go
  • Changed Target 0 to Target 1 in the TARGET_AUTO_ACK_1 bit descriptionGo
  • Changed Target 0 to Target 2 in the TARGET_AUTO_ACK_2 bit descriptionGo
  • Changed Target 0 to Target 3 in the TARGET_AUTO_ACK_3 bit descriptionGo
  • Changed Target 0 to Target 4 in the TARGET_AUTO_ACK_4 bit descriptionGo
  • Changed Target 0 to Target 5 in the TARGET_AUTO_ACK_5 bit descriptionGo
  • Changed Target 0 to Target 6 in the TARGET_AUTO_ACK_6 bit descriptionGo
  • Changed Target 0 to Target 7 in the TARGET_AUTO_ACK_7 bit descriptionGo
  • Changed CRC_ERR bit description in GENERAL_STATUS to match CRC_ERR_CLR register name Go
  • Changed the CNTRL_ERR_HSRQST_2 bit descriptionGo
  • Changed Typical Applications Coaxial Diagram captionGo
  • Added PIN(S) column to Table 7-3 Go
  • Changed large bulk capacitor typical range lower limit from 50µF to 47µF, removed mentions of dedicated power plane and tantalum capacitors, and changed recommended power rating for capacitors in layout guidelines Go
  • Changed recommended CSI-2 guidelines on matching trace lengths and routing to help trace impedanceGo
  • Changed routing guidelines for the DOUT+ and DOUT– pins Go
  • Added new links to the Related Documentation sectionGo