SNOSCY4E March   2015  – October 2018 LMG5200

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Mismatch Measurement
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Inputs
      2. 8.3.2 Start-up and UVLO
      3. 8.3.3 Bootstrap Supply Voltage Clamping
      4. 8.3.4 Level Shift
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VCC Bypass Capacitor
        2. 9.2.2.2 Bootstrap Capacitor
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Information

8.3.2 Start-up and UVLO

The LMG5200 has an UVLO on both the VCC and HB (bootstrap) supplies. When the VCC voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs from being partially turned on. Also, if there is insufficient VCC voltage, the UVLO actively pulls the high- and low-side GaN FET gates low. When the HB to HS bootstrap voltage is below the UVLO threshold of 3.2 V, only the high-side GaN FET gate is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid chattering.

Table 1. VCC UVLO Feature Logic Operation

CONDITION (VHB-HS > VHBR for all cases below) HI LI SW
VCC - VSS < VCCR during device start-up H L Hi-Z
VCC - VSS < VCCR during device start-up L H Hi-Z
VCC - VSS < VCCR during device start-up H H Hi-Z
VCC - VSS < VCCR during device start-up L L Hi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-up H L Hi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-up L H Hi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-up H H Hi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-up L L Hi-Z

Table 2. VHB-HS UVLO Feature Logic Operation

CONDITION (VCC > VCCR for all cases below) HI LI SW
VHB-HS < VHBR during device start-up H L Hi-Z
VHB-HS < VHBR during device start-up L H PGND
VHB-HS < VHBR during device start-up H H PGND
VHB-HS < VHBR during device start-up L L Hi-Z
VHB-HS < VHBR - VHB(hyst) after device start-up H L Hi-Z
VHB-HS < VHBR - VHB(hyst) after device start-up L H PGND
VHB-HS < VHBR - VHB(hyst) after device start-up H H PGND
VHB-HS < VHBR - VHB(hyst) after device start-up L L Hi-Z