SNOSDE5A December   2021  – May 2022 LM74502 , LM74502H

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage
      2. 8.3.2 Charge Pump (VCAP)
      3. 8.3.3 Gate Driver (GATE, SRC)
        1. 8.3.3.1 Inrush Current Control
      4. 8.3.4 Enable (EN/UVLO)
      5. 8.3.5 Overvoltage Protection (OV)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Conduction Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Design Considerations
        2. 9.2.2.2 MOSFET Selection
        3. 9.2.2.3 Overvoltage Protection
        4. 9.2.2.4 Charge Pump VCAP, Input and Output Capacitance
      3. 9.2.3 Application Curves
    3. 9.3 Input Surge Stopper Using LM74502, LM74502H
      1. 9.3.1 VS Capacitance, Resistor R1 and Zener Clamp (DZ)
      2. 9.3.2 Overvoltage Protection
      3. 9.3.3 MOSFET Selection
    4. 9.4 Fast Turn-On and Turn-Off High Side Switch Driver Using LM74502H
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6.6 Switching Characteristics

TJ = –40°C to +125°C; typical values at TJ = 25°C, V(VS) = 12 V, CIN = C(VCAP) = COUT = 0.1 µF, V(EN/UVLO) = 3.3 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENTDLY EN high to Gate Turn On delay V(VCAP) > V(VCAP UVLOR), V(EN/UVLO) > V(EN_UVLOR) to V(GATE-SRC) > 5 V, C(GATE-SRC) = 4.7 nF LM74502H 75 110 µs
tUVLO_OFF(deg)_GATE GATE Turnoff delay during EN/UVLO V(EN/UVLO) ↓ to V(GATE-SRC) < 1 V, C(GATE-SRC) = 4.7 nF 2 µs
tOVP_OFF(deg)_GATE GATE Turnoff delay  during OV V(OV) ↑ to V(GATE-SRC) < 1 V, C(GATE-SRC) = 4.7 nF 0.6 1 µs
tOVP_ON(deg)_GATE GATE Turnon delay during OV V(OV) ↓ to V(GATE-SRC) > 5 V, C(GATE-SRC) = 4.7 nF
LM74502H		 5 10 µs