SNVA856B May   2020  – October 2022 LM63615-Q1 , LM63625-Q1 , LM63635-Q1 , LMR33620 , LMR33620-Q1 , LMR33630 , LMR33630-Q1 , LMR33640 , LMR36006 , LMR36015 , TPS54360B , TPS54560B

 

  1.   Working With Inverting Buck-Boost Converters
  2.   Trademarks
  3. 1 Introduction
  4. 2 Inverting Buck-Boost Converter
  5. 3 Basic Operation
  6. 4 Operating Considerations of a Buck Based Inverting Buck-Boost
    1. 4.1 Voltage Stress
    2. 4.2 Current Stress
    3. 4.3 Power Loss and Efficiency
    4. 4.4 Small Signal Behavior
      1. 4.4.1 Measuring IBB Bode Plots
      2. 4.4.2 Testing Load Transients on an IBB
      3. 4.4.3 Simulation
  7. 5 Component Selection for the IBB
    1. 5.1 Inductor Selection
    2. 5.2 Capacitor Selection
    3. 5.3 External Feed-back Divider
  8. 6 General Considerations
  9. 7 Auxiliary Functions
    1. 7.1 Enable Input Level Shift
    2. 7.2 Synchronizing Input Level Shift
    3. 7.3 Power-Good Flag Level Shift
    4. 7.4 Output Clamp
    5. 7.5 Output Noise Filtering
  10. 8 Design Examples
    1. 8.1 Converting +12 V to –5 V at 3 A
    2. 8.2 Converting +5 V to –5 V at 1 A
  11. 9 Summary
  12. 10References
  13. 11Revision History

7.2 Synchronizing Input Level Shift

Some regulators have a synchronizing input for locking the switching frequency to the system clock. One of the level shifters shown in Figure 7-2 can be used to provide this function.

GUID-911BD07F-E609-4136-AFB7-FB1ED6BDEDD4-low.gif Figure 7-2 Synchronization Level Shifters

The lower schematic shows a simple solution, but requires a low impedance drive signal. The solution in the upper schematic although more complex allows the use of ordinary logic drive. Also, this solution requires that the SYNC input can withstand VIN + |VOUT|. In all cases the RC time constant should be much longer than the switching period.