SNVA912A January   2020  – April 2021 REF34-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 DBV-6 Package
    2. 2.2 DBV-5 Package
    3. 2.3 DGK-8 Package
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 DBV-6 Package
    2. 4.2 DBV-5 Package
    3. 4.3 DGK-8 Package

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the REF34-Q1 (DBV-6, DBV-5 and DGK-8 packages). The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-2 through Table 4-13 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • 10uF capacitor connected to Vout
  • 1uF capacitor connected to Vin