SNVA990 August 2020 – MONTH LM25183 , LM25183-Q1 , LM25184 , LM25184-Q1
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This document contains information for LM25183, LM25184, LM25183-Q1, and LM25184-Q1 (WSON package) to aid in a functional safety system design. Information provided are:
Figure 1-1 shows the device functional block diagram for reference.
LM25183, LM25184, LM25183-Q1, and LM25184-Q1 were developed using a quality-managed development process, but were not developed in accordance with the IEC 61508 or ISO 26262 standards.
This section provides Functional Safety Failure In Time (FIT) rates for LM25183, LM25184, LM25183-Q1, and LM25184-Q1 based on two different industry-wide used reliability standards:
FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) |
---|---|
Total Component FIT Rate | 13 |
Die FIT Rate | 7 |
Package FIT Rate | 6 |
The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:
Table | Category | Reference FIT Rate | Reference Virtual TJ |
---|---|---|---|
5 | CMOS,
BICMOS Digital, analog / mixed | 25 FIT | 55°C |
The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.
The failure mode distribution estimation for LM25183, LM25184, LM25183-Q1, and LM25184-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
Die Failure Modes | Failure Mode Distribution (%) |
---|---|
No SW output | 45% |
SW output not in specification – voltage or timing | 40% |
SW power FET stuck on | 5% |
EN/UVLO false trip or fails to trip | 5% |
Short circuit to any two pins | 5% |
The FMD in Table 3-1 excludes short circuit faults across the isolation barrier. Faults for short circuit across the isolation barrier can be excluded according to ISO 61800-5-2:2016 if the following requirements are fulfilled:
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.
This section provides a Failure Mode Analysis (FMA) for the pins of the LM25183, LM25184, LM25183-Q1, and LM25184-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Class | Failure Effects |
---|---|
A | Potential device damage that affects functionality |
B | No device damage, but loss of functionality |
C | No device damage, but performance degradation |
D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the LM25183, LM25184, LM25183-Q1, and LM25184-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LM25183, LM25184, LM25183-Q1, and LM25184-Q1 data sheets.
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
SW | 1 | VOUT = 0 V; Damage to transformer | A |
FB | 2 | VOUT = 0 V; Damage VIN to FB | A |
VIN | 3 | VOUT = 0 V | B |
EN/UVLO | 4 | VOUT = 0 V; Shutdown operation | B |
SS/BIAS | 5 | VOUT = 0 V if short during start-up. VOUT normal if short during steady-state | B |
TC | 6 | Temperature compensation disabled; VOUT target will be slightly different due to Rtc||Rset | C |
RSET | 7 | VOUT = ISW-PEAK*tOFF*Rload*NPS/240 μs; 120 μs switching | B |
GND | 8 | Normal operation. | D |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
SW | 1 | VOUT = 0 V; No switching | B |
FB | 2 | VOUT = 0 V; 120 μs switching | B |
VIN | 3 | VOUT = 0 V | B |
EN/UVLO | 4 | Shutdown or Regulating since EN is high impedance | B |
SS/BIAS | 5 | VOUT regulating; Internal SS only | C |
TC | 6 | VOUT regulating; Temperature compensation disabled | C |
RSET | 7 | VOUT = 0 V; VOUT cannot be sensed | B |
GND | 8 | Floating GND | B |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
SW | 1 | VOUT = 0 V; Damage VIN to FB diode | A |
FB | 2 | VOUT = 0 V; VOUT cannot be sensed | B |
VIN | 3 | VOUT regulating; Always in ACTIVE mode | C |
EN/UVLO | 4 | -- | -- |
SS/BIAS | 5 | Current limit threshold will be lower | B |
TC | 6 | VOUT = ISW-PEAK*tOFF*Rload*NPS/240 μs depending on TC; VOUT cannot be sensed | B |
RSET | 7 | VOUT = ISW-PEAK*tOFF*Rload*NPS/240 μs depending on TC; VOUT cannot be sensed | B |
GND | 8 | -- |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
SW | 1 | VOUT = 0 V; Damage SW to GND | A |
FB | 2 | VOUT = 0 V; VOUT cannot be sensed | B |
VIN | 3 | Normal Operation | D |
EN/UVLO | 4 | VOUT regulating; Always in ACTIVE mode | C |
SS/BIAS | 5 | Damage to 15 V ESD on SS/BIAS | A |
TC | 6 | Damage to 5 V ESD on TC | A |
RSET | 7 | Damage to 5 V ESD on RSET | A |
GND | 8 | VOUT = 0 V | B |