SNVAA63 March   2023 TPSM365R6

 

  1.   Abstract
  2.   Trademarks
  3. 1Inverting Buck-Boost Topology
    1. 1.1 Concept
    2. 1.2 Output Current Calculations
    3. 1.3 VIN and VOUT Range in Inverting Configuration
  4. 2Design Considerations
    1. 2.1 Additional Bypass Capacitor and Schottky Diode
    2. 2.2 Start-up Behavior and Switching Node Consideration
  5. 3External Components
    1. 3.1 Capacitor Selection
    2. 3.2 System Loop Stability
  6. 4Typical Performance
  7. 5Digital Pin Configurations
    1. 5.1 Digital Input Pin
    2. 5.2 Power-Good Pin
  8. 6Conclusion
  9. 7References

5.2 Power-Good Pin

The TPSM365R6 has a built-in power-good (PGOOD) function to indicate whether the output voltage has reached its target voltage or not. The PGOOD pin is an open-drain output that requires a pullup resistor. In the standard buck configuration, the PGOOD pin would be referenced to the TPSM365R6 IC GND pin, and output a high signal when the device reaches the proper output voltage. However, in the inverting buck boost configuration, as the TPSM365R6’s IC GND pin turns into the -VOUT pin, the PGOOD pin will also be referenced to –VOUT. The device then pulls PGOOD to –VOUT when it is low.

This behavior can cause difficulties in reading the state of the PG pin, because in some applications the IC detecting the polarity of the PGOOD pin may not be able to withstand negative voltages. The level shifter circuit alleviates any difficulties associated with the PGOOD pin voltages by eliminating the negative output signals of the PGOOD pin. If the PGOOD pin functionality is not needed, it can be left floating or connected to –VOUT. Note, to avoid violating the absolute maximum rating, the PGOOD pin must not be driven more than 20 V above the negative output voltage. Figure 5-4 shows the required connections to make the PGOOD pin level shifter.

Figure 5-4 PGOOD Pin Level Shifter
Table 5-2 Transistor States During PGOOD Level Shifter Behavior
POWER NOT GOOD GOOD
Q1 ON OFF
Q2 OFF ON
Q3 ON OFF
SYS_PG LOW HIGH

Internally, the PGOOD pin is connected to an N-channel MOSFET (Q1). By tying the PGOOD pin to the gate of Q2, Q2 will turn off when the PGOOD pin is pulled to -VOUT, as no potential difference will be detected across Q2’s gate and source. As a result, Q3 will turn on, because the potential difference between it’s gate and source will be VEXT. Note that the VEXT voltage must provide enough potential difference between Q3's gate and source to turn on Q3. The outgoing SYS_PG signal is then pulled to SYS_GND.

When –VOUT has reached its target value, Q1 turns on, which pulls the gate of Q2 to SYS_GND. Consequently, Q2 turns on as its gate voltage is higher than its source voltage. This pulls the gate of Q3 to -VOUT, turning Q3 off as its gate is now at a lower potential than its source, which is tied to SYS_GND. With Q3 off, the outgoing SYS_PG signal is pulled to VEXT.

The output voltage activates the PGOOD pin level shifter circuit and swings the output signal, SYS_PG from VEXT to SYS_GND, properly showing if the device’s output is at its targeted output voltage or not. Figure 5-5 and Figure 5-6 show the behavior of the device with the PGOOD pin level shifter installed.

Figure 5-5 PG Pin Level Shifter on Start-Up
Figure 5-6 PG Pin Level Shifter on Shutdown