SNVS256E November   2003  – October 2024 LP3943

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
    1.     Pin Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface (SCL and SDA Pins) Timing Requirements
    7. 5.7 Typical Characteristic
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 I2C Data Validity
      2. 6.5.2 I2C START and STOP Conditions
      3. 6.5.3 Transferring Data
      4. 6.5.4 Auto Increment
    6. 6.6 Register Maps
      1. 6.6.1 Binary Format for Input Registers (Read-only)—Address 0x00 and 0x01
      2. 6.6.2 Binary Format for Frequency Prescaler and PWM Registers — Address 0x02 to 0x05
      3. 6.6.3 Binary Format for Selector Registers — Address 0x06 to 0x09
  8.   Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Reducing IQ When LEDs are OFF
      3. 7.2.3 Application Curve
    3. 7.3 System Examples
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Community Resources
    3. 7.3 Trademarks
  10. 8Revision History
  11.   Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

Unless otherwise noted, VDD = 5.5V. Typical values and limits apply for TJ = 25°C. Minimum and maximum limits apply over the entire junction temperature range for operation, TJ = −40°C to +125°C.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VDD Supply voltage 2.3 5 5.5 V
IQ Supply current No load 350 550 µA
Standby 2 5
ΔIQ Additional standby current VDD = 5.5V, every LED pin at 4.3V 2 mA
VPOR Power-On Reset voltage 1.8 1.96 V
tw Reset pulse width 10 ns
LED
VIL Low level input voltage −0.5 0.8 V
VIH High level input voltage 2 5.5 V
IOL Low level output current(2) VOL = 0.4V, VDD = 2.3V 9 mA
VOL = 0.4V, VDD = 3V 12
VOL = 0.4V, VDD = 5V 15
VOL = 0.7V, VDD = 2.3V 15
VOL = 0.7V, VDD = 3V 20
VOL = 0.7V, VDD = 5V 25
ILEAK Input leakage current VDD = 3.6V, VIN = 0V or VDD −1 1 µA
CI/O Input/output capacitance See(3) 2.6 5 pF
ALL DIGITAL PINS (EXCEPT SCL AND SDA PINS)
VIL LOW level input voltage −0.5 0.8 V
VIH HIGH level input voltage 2 5.5 V
ILEAK Input leakage current −1 1 µA
CIN Input capacitance VIN = 0V(3) 2.3 5 pF
I2C INTERFACE (SCL AND SDA PINS)
VIL LOW level input voltage –0.5 0.3VDD V
VIH HIGH level input voltage 0.7VDD 5.5 V
VOL LOW level output voltage 0 0.2VDD V
IOL LOW level output current VOL = 0.4V 3 6.5 mA
IQ_SCL/SDA SCL/SDA to VDD capable current 100 µA
ƒCLK Clock frequency 400 kHz
(1) Limits are ensured. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) Each LED pin must not exceed 25 mA and each octal (LED0–LED7; LED8–LED15) must not exceed 100 mA. The package must not exceed a total of 200 mA.
(3) Verified by design.