SNVSBU4E
June 2022 – August 2024
LM5177
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
Handling Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Typical Characteristics
6
Parameter Measurement Information
6.1
Gate Driver Rise Time and Fall Time
6.2
Gate Driver Dead (Transition) Time
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Power-On Reset (POR System)
7.3.2
Buck-Boost Control Scheme
7.3.2.1
Boost Mode
7.3.2.2
Buck Mode
7.3.2.3
Buck-Boost Mode
7.3.3
Power Save Mode
7.3.4
Supply Voltage Selection – VMAX Switch
7.3.5
Enable and Undervoltage Lockout
7.3.6
Oscillator Frequency Selection
7.3.7
Frequency Synchronization
7.3.8
Voltage Regulation Loop
7.3.9
Output Voltage Tracking
7.3.10
Slope Compensation
7.3.11
Configurable Soft Start
7.3.12
Peak Current Sensor
7.3.13
Current Monitoring and Current Limit Control Loop
7.3.14
Short Circuit - Hiccup Protection
7.3.15
nFLT Pin and Protections
7.3.16
Device Configuration Pin
7.3.17
Dual Random Spread Spectrum – DRSS
7.3.18
Gate Driver
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Custom Design with WEBENCH Tools
8.2.2.2
Frequency
8.2.2.3
Feedback Divider
8.2.2.4
Inductor and Current Sense Resistor Selection
8.2.2.5
Slope Compensation
8.2.2.6
Output Capacitor
8.2.2.7
Input Capacitor
8.2.2.8
UVLO Divider
8.2.2.9
Soft-Start Capacitor
8.2.2.10
MOSFETs QH1 and QL1
8.2.2.11
MOSFETs QH2 and QL2
8.2.2.12
Frequency Compensation
8.2.2.13
External Component Selection
8.2.3
Application Curves
8.3
System Examples
8.3.1
Bi-Directional Power Backup
8.3.2
Parallel (Multiphase) Operation
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.1.1
Power Stage Layout
10.1.2
Gate Driver Layout
10.1.3
Controller Layout
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.1.2
Development Support
11.1.2.1
Custom Design with WEBENCH Tools
11.2
Receiving Notification of Documentation Updates
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Revision History
13
Mechanical, Packaging, and Orderable Information
8.2.3
Application Curves
Figure 8-2
Start-up waveform standby to active operation
(MODE = V
(VCC)
, V
o
= 12 V, I
o
= 0 A, V
(VIN)
= 12 V)
Figure 8-4
Inductor current buck-boost operation
(MODE = V
(VCC)
, V
o
= 12 V, I
o
= 0 A, V
(VIN)
= 12 V)
Figure 8-6
Inductor current boost operation
(MODE = 0 V, V
o
= 12 V, I
o
= 10 mA, V
(VIN)
= 6 V)
Figure 8-8
Inductor current buck operation
(MODE = 0 V, V
o
= 12 V, I
o
= 10 mA, V
(VIN)
= 24 V)
Figure 8-10
Efficiency Versus I
O
(MODE = 0V V
o
= 12 V)
Figure 8-12
Efficiency Versus I
O
in Boost Mode
(V
IN
= 5 V, V
o
= 12 V)
Figure 8-14
Efficiency Versus I
O
in Buck Mode
V
IN
= 24 V, V
o
= 12 V)
Figure 8-3
Inductor current boost operation
(MODE = V
(VCC)
, V
o
= 12 V, I
o
= 0 A, V
(VIN)
= 6 V)
Figure 8-5
Inductor current buck operation
(MODE = V
(VCC)
, V
o
= 12 V, I
o
= 0 A, V
(VIN)
= 24 V)
Figure 8-7
Inductor current buck-boost operation
(MODE = 0 V, V
o
= 12 V, I
o
= 10 mA, V
(VIN)
= 12 V)
Figure 8-9
Input voltage ramp from 6V to 24V
(MODE = V
(VCC)
, V
o
= 12 V, I
o
= 6A
Figure 8-11
Efficiency Versus I
O
(MODE = VCC V
o
= 12 V)
Figure 8-13
Efficiency Versus I
O
in Buck-Boost Mode
V
IN
= 12 V, V
o
= 12 V)
Figure 8-15
Efficiency Versus V
IN
(V
o
= 12 V, I
O
= 6 A)