SNVSC77 December   2024 LM5125-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin)
      2. 6.3.2  Switching Frequency and Synchronization (SYNCIN)
      3. 6.3.3  Dual Random Spread Spectrum (DRSS)
      4. 6.3.4  Operation Modes (BYPASS, DEM, FPWM)
      5. 6.3.5  Dual- and Multi-phase Operation
      6. 6.3.6  BIAS (BIAS-pin)
      7. 6.3.7  Soft Start (SS-pin)
      8. 6.3.8  VOUT Programming (VOUT, ATRK, DTRK)
      9. 6.3.9  Protections
      10. 6.3.10 VOUT Overvoltage Protection (OVP)
      11. 6.3.11 Thermal Shutdown (TSD)
      12. 6.3.12 Power-Good Indicator (PGOOD-pin)
      13. 6.3.13 Current Sensing, Peak Current Limit, and Slope Compensation (CSP1, CSP2, CSN1, CSN2)
      14. 6.3.14 Current Sense Programming (CSP1, CSP2, CSN1, CSN2)
      15. 6.3.15 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LOx, HOx, HBx-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Determine the Total Phase Number
        2. 7.2.3.2  Determining the Duty Cycle
        3. 7.2.3.3  Timing Resistor RT
        4. 7.2.3.4  Inductor Selection Lm
        5. 7.2.3.5  Current Sense Resistor Rcs
        6. 7.2.3.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.3.7  Low-Side Power Switch QL
        8. 7.2.3.8  High-Side Power Switch QH and Additional Parallel Schottky Diode
        9. 7.2.3.9  Snubber Components
        10. 7.2.3.10 Vout Programming
        11. 7.2.3.11 Input Current Limit (ILIM/IMON)
        12. 7.2.3.12 UVLO Divider
        13. 7.2.3.13 Soft Start
        14. 7.2.3.14 CFG Settings
        15. 7.2.3.15 Output Capacitor Cout
        16. 7.2.3.16 Input Capacitor Cin
        17. 7.2.3.17 Bootstrap Capacitor
        18. 7.2.3.18 VCC Capacitor CVCC
        19. 7.2.3.19 BIAS Capacitor
        20. 7.2.3.20 VOUT Capacitor
        21. 7.2.3.21 Loop Compensation
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
        2. 7.2.4.2 Steady State Waveforms
        3. 7.2.4.3 Step Load Response
        4. 7.2.4.4 Sync Operation
        5. 7.2.4.5 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2.     85

7.2.3.11 Input Current Limit (ILIM/IMON)

In audio applications, the transient power can be high. For this application, 1000W is selected as peak output power. But the average power is typically much lower than the peak power. 300W is selected as average power. With proper ILIM/IMON setting, the average input current can be limited to less than 300W while allowing 1000W peak for 100ms. When the average current loop is triggered, VOUT drops till the input and output power is balanced.

The per phase input current at average output power and typical input voltage can be found as:

Equation 48. Iavg=Pavg_total2×η×Vin_typ=11.0A

13A is selected as the average input current limit.

Equation 49. Ilim=13A

The current out of ILIM/IMON at can be found as:

Equation 50. I M O N _ l i m = 2 × R c s × I l i m × G I M O N + I O F F S E T = 2 × 1.5 m Ω × 13 A × 0.333 m A / V + 4 μ A = 21 μ A

RILIM can be calculated as:

Equation 51. RIMON=VILIMIMON=1V21μA=47.6kΩ

A standard value of 47.5kΩ is chosen for RIMON.

As shown in Figure 7-8, CIMON and Rc can be used to create a proper delay before the average current loop is triggered.

LM5125-Q1 ILIM/IMON Pin Configuration Figure 7-8 ILIM/IMON Pin Configuration

In this application, 100ms delay at twice rated power is required.

At zero load, current out of ILIM/IMON can be found as:

Equation 52. IMON_0A=2×IOFFSET=8μA

The ILIM/IMON voltage at zero load can be calculated as:

Equation 53. VIMON_0A=RIMON×IMON_0A=0.38V

At twice rated power, current out of ILIM/IMON can be found as:

Equation 54. IMON_tr=2×Rcs×2×Ilim×GIMON+IOFFSET=2×1.5mΩ×26A×0.333mA/V+4μA=34μA

CIMON can be determined by:

Equation 55. CIMON=tdelayRIMON×lnRIMON×IMON_tr-VIMON_0ARIMON×IMON_tr-VILIM=3.0μF

A standard value of 3.3μF is chosen for CIMON.

Rc can be determined by:

Equation 56. Rc=120π×CIMON=4.8k

A standard value of 4.99kΩ is chosen for Rc.