SNVSCD2 September   2024 LM704A0-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN)
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC, BIAS, VDDA)
      3. 6.3.3  Enable (EN)
      4. 6.3.4  Power-Good Monitor (PG)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Dual Random Spread Spectrum (DRSS)
      7. 6.3.7  Soft Start
      8. 6.3.8  Output Voltage Setpoint (FB)
      9. 6.3.9  Minimum Controllable On-Time
      10. 6.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
      11. 6.3.11 Slope Compensation
      12. 6.3.12 Shunt Current Sensing
      13. 6.3.13 Hiccup Mode Current Limiting
      14. 6.3.14 Device Configuration (CONFIG)
      15. 6.3.15 Single-Output Dual-Phase Operation
      16. 6.3.16 Pulse Frequency Modulation (PFM) / Synchronization
      17. 6.3.17 Thermal Shutdown (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Active Mode
      4. 6.4.4 Sleep Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
      3. 7.1.3 Maximum Ambient Temperature
        1. 7.1.3.1 Derating Curves
    2. 7.2 Typical Applications
      1. 7.2.1 Design 1 – High Efficiency, Wide Input, 400kHz Synchronous Buck Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 7.2.1.2.3 Buck Inductor
          4. 7.2.1.2.4 Current-Sense Resistance
          5. 7.2.1.2.5 Output Capacitors
          6. 7.2.1.2.6 Input Capacitors
          7. 7.2.1.2.7 Frequency Set Resistor
          8. 7.2.1.2.8 Feedback Resistors
          9. 7.2.1.2.9 Compensation Components
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Design 2 – High Efficiency 24V to 3.3V 400kHz Synchronous Buck Regulator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Thermal Design and Layout
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 PCB Layout Resources
        2. 8.2.1.2 Thermal Design Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

5.5 Electrical Characteristics

TJ = –40°C to +150°C. Typical values are at TJ = 25°C and VIN = 12V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY (VIN)
IQ-SD VIN shutdown  current Non-switching, VEN = 0V, VFB = VREF + 50mV, TJ = 25°C 2.3 4 µA
Non-switching, VEN = 0V, VFB = VREF + 50mV, TJ = 125°C 2.3 8 µA
IQ-SBY VIN standby  current (1) Non-switching,  0.5V ≤ VEN ≤ 1V,  External COMP, RCONFIG = 29.4kΩ 350 µA
IQ-SLEEP1-12V VIN sleep current, 3.3V fixed output, no load VEN = 5V, VIN = 12V, VBIAS = 0V, VVOUT = 3.3V, no-load, non-switching,  VPFM/SYNCIN = 5V, RFB = 0Ω to VDDA 10.8 µA
IQ-SLEEP2-12V VIN sleep current, 5V fixed output, no load VEN = 5V, VIN = 12V, VBIAS = 5V, VVOUT = 5V, no-load, non-switching,  VPFM/SYNCIN = 5V, RFB = 24.9kΩ to VDDA 12.2 36 µA
ENABLE (EN / UVLO)
VSBY-TH Shutdown-to-standby threshold voltage VEN/UVLO rising 0.55 V
VEN-TH Enable voltage rising threshold VEN/UVLO rising 0.95 1.0 1.05 V
VEN-HYS Enable voltage hysteresis 0.1 V
INTERNAL LDO (VCC)
VVCC1 VCC regulation voltage IVCC = 50mA, RFB = 0Ω or 24.9kΩ 4.5 5 5.5 V
VVCC2 VCC regulation voltage IVCC = 50mA 7 8 8.5 V
INTERNAL LDO (VDDA)
VVDDA VDDA regulation voltage IVDD = 5mA 4.75 5 5.25 V
IVDDA-CL VDDA short-circuit current limit VDDA = 4.5V 10 15 20 mA
EXTERNAL BIAS (BIAS)
VBIAS-TH1 VIN to VBIAS switchover rising threshold, 12V fixed or adjustable output RFB = 49.9kΩ 8.8 9.1 9.3 V
VBIAS-TH2 VIN to VBIAS switchover rising threshold, 3.3V or 5V fixed output RFB = 0Ω or 24.9kΩ 4.3 4.6 4.8 V
VBIAS-HYS VIN to VBIAS switchover hysteresis 550 mV
REFERENCE VOLTAGE (FB)
VFB Regulated FB voltage 794 800 806 mV
OUTPUT VOLTAGE (VOUT)
VOUT1 3.3V output voltage setpoint RFB = 0Ω 3.267 3.3 3.333 V
VOUT2 5V output voltage setpoint
 		 RFB = 24.9kΩ 4.95 5.0 5.05 V
VOUT3 12V output voltage setpoint RFB = 49.9kΩ 11.88 12 12.12 V
ERROR AMPLIFIER (EXTCOMP)
gm-EXTERNAL EA transconductance external compensation FB to COMP 970 1200 µS
gm-NTERNAL EA transconductance internal compensation (1) FB to COMP, EXTCOMP 100kΩ to VDDA 30 µS
IFB Error amplifier input bias current 75 nA
VCOMP-CLAMP COMP clamp voltage VFB = 0V 2.1 V
ICOMP-SRC EA source current VCOMP = 1V, VFB = 0.65V 170 µA
ICOMP-SINK EA sink current VCOMP = 1V, VFB = 0.95V 170 µA
PULSE FREQUENCY MODULATION (PFM/SYNCIN)
VIL-SYNCIN PFM/SYNCIN input threshold low 0.8 V
VIH(SYNCIN) PFM/SYNCIN  input threshold high 1.17 V
fSYNC1 Synchronization frequency range (220kHz) RRT = 100kΩ, ±20 % of the nominal oscillator frequency 176 264 kHz
fSYNC2 Synchronization frequency range (2.2MHz) RRT = 10kΩ, ±20 % of the nominal oscillator frequency 1.76 2.64 MHz
tSYNC-TON-MIN Minimum positive pulse width of external synchronization signal RRT = 10kΩ 20 ns
tSYNC-TOFF-MIN Minimum negative pulse width of external synchronization signal RRT = 10kΩ 200 ns
tSYNCIN-SW Delay from PFM falling edge to SW rising edge (1) 35 ns
tPFM-FILTER SYNCIN to PFM mode 15 75 µs
DUAL RANDOM SPREAD SPECTRUM (DRSS)
ΔfC Distance from the switching frequency 8 %
fm Modulation frequency 10 kHz
SWITCHING FREQUENCY (SW)
fSW1 Switching frequency 1 RRT = 100kΩ to AGND  200 220 240 kHz
fSW2 Switching frequency 2 RRT = 49.9kΩ to AGND  400 440 480 kHz
fSW3 Switching frequency 3 RRT = 22.1kΩ to AGND  0.85 0.95 1.05 MHz
fSW4 Switching frequency 4 RRT = 9.09kΩ to AGND  2 2.2 2.4 MHz
tON-MIN Minimum on-time(1) 25 ns
tOFF-MIN Minimum off-time 88 126 ns
POWER GOOD (PG)
VPG-UV Power-Good UV trip level Falling with respect to the regulated voltage 90 % 92 %  94%
VPG-OV Power-Good OV trip level  Rising with respect to the regulation voltage 108 % 110 % 112 %
VPG-UV-HYST Power-Good UV hysteresis  Falling with respect to the regulated output 3.4 %
VPG-OV-HYST Power-Good OV hysteresis  Raising with respect to the regulated output 3.4 %
tPG-DEGLITCH Power-Good deglitch filter time VOUT falling or rising 25 µs
VOL-PG Power-Good voltage Open collector, IPG = 2mA 0.4 V
SYNCHRONIZATION OUTPUT (SYNCOUT)
VSYNCOUT-LTH SYNCOUT low state voltage threshold RCONFIG  = 54.9kΩ or 71.5kΩ, ISYNCOUT = 2mA 0.4 V
VSYNCOUT-HTH SYNCOUT high state voltage threshold RCONFIG  = 54.9kΩ or 71.5kΩ, ISYNCOUT = −2mA 2.0 V
STARTUP (SOFT START)
tSS Internal fixed soft-start time 1.9 2.8 4.4 ms
INTERNAL HICCUP MODE
tHIC-DLY HICCUP mode activation delay VISNS+ − VVOUT > 60mV 512 CYCLES
tHIC-DURATION HICCUP mode fault duration VISNS+ − VVOUT > 60mV 16384 CYCLES
OVERCURRENT PROTECTION (OCP)
VCS-TH CS voltage threshold Measured from ISNS+ to VOUT 50 56 62 mV
tDELAY-CS CS delay to output 75 ns
GCS CS amplifier gain (1) 10 V/V
IBIAS-CS CS amplifier input bias current (1) 0.35 µA
VCS-TH-NEG CS negative voltage threshold 30 mV
THERMAL SHUTDOWN (TSD)
TJ-SD Thermal shutdown threshold (1) Temperature rising 175 °C
TJ-HYS Thermal shutdown hysteresis (1) 15 °C
(1) Specified by design. Not production tested.