SNVSCD4 September   2024 LM70660 , LM706A0

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN)
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC, BIAS, VDDA)
      3. 6.3.3  Enable (EN)
      4. 6.3.4  Power-Good Monitor (PG)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Dual Random Spread Spectrum (DRSS)
      7. 6.3.7  Soft Start
      8. 6.3.8  Output Voltage Setpoint (FB)
      9. 6.3.9  Minimum Controllable On-Time
      10. 6.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
      11. 6.3.11 Slope Compensation
      12. 6.3.12 Shunt Current Sensing
      13. 6.3.13 Hiccup Mode Current Limiting
      14. 6.3.14 Device Configuration (CONFIG)
      15. 6.3.15 Single-Output Dual-Phase Operation
      16. 6.3.16 Pulse Frequency Modulation (PFM) / Synchronization
      17. 6.3.17 Thermal Shutdown (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Active Mode
      4. 6.4.4 Sleep Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
      3. 7.1.3 Maximum Ambient Temperature
        1. 7.1.3.1 Derating Curves
    2. 7.2 Typical Applications
      1. 7.2.1 Design 1 – High Efficiency, Wide Input, 400kHz Synchronous Buck Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 7.2.1.2.3 Buck Inductor
          4. 7.2.1.2.4 Current-Sense Resistance
          5. 7.2.1.2.5 Output Capacitors
          6. 7.2.1.2.6 Input Capacitors
          7. 7.2.1.2.7 Frequency Set Resistor
          8. 7.2.1.2.8 Feedback Resistors
          9. 7.2.1.2.9 Compensation Components
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Design 2 – High Efficiency 24V to 3.3V 400kHz Synchronous Buck Regulator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Thermal Design and Layout
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 PCB Layout Resources
        2. 8.2.1.2 Thermal Design Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

4 Pin Configuration and Functions

Figure 4-1 RRX Package, 29-Pin VQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 VIN4 P Converter input pins to the drain of the high-side power MOSFET and the VCC regulator (VIN6). Connect to the input supply and the input filter capacitors. The path from the VIN pin to the input capacitors must be as short as possible.
2 VIN5 P
3 VIN6 P
4 CBOOT P High-side driver supply for the bootstrap gate drive. Connect a 47nF bootstrap capacitor between the CBOOT and SW4 pins. If VCC = 8V is selected, add a 1Ω resistor in series with the bootstrap capacitor.
5 SW4 P Switch pin. Connect a 47nF bootstrap capacitor between the CBOOT and SW4 pins. This pin is internally connected to the switch pins SW1, SW2, and SW3. There is no need to route this pin to the other switch pins on a PCB.
6 BIAS P Optional input for an external bias supply. If configured for 3.3V fixed VOUT, connect the BIAS pin to an external bias supply from 5V to 30V. If configured for 5V fixed VOUT, connect the BIAS pin to the VOUT node or an external bias supply from 5V to 30V. If configured for 12V fixed or an adjustable VOUT, connect the BIAS pin to the VOUT node or an external bias supply from 10V to 30V. If the output voltage is above 30V and no external supply is used, tie the BIAS pin to GND.
7 PG / SYNCOUT O Power-Good / Sync Output pin. This pin is an open-collector output that goes low if VOUT is outside of the specified regulation window. PG / SYNCOUT can also be used as a synchronization output to synchronize the internal oscillator of the secondary device to the oscillator of the primary device.
8 PFM / SYNCIN I PFM / FPWM mode selection and synchronization input pin. Connect the PFM / SYNCIN pin to VDDA to enable diode emulation mode. Connect the PFM / SYNCIN pin to AGND to operate in Forced PWM (FPWM) mode with continuous conduction at light loads. The PFM / SYNCIN pin can also be used as a synchronization input to synchronize the internal oscillator to an external clock.
9 EN / UVLO I Enable / undervoltage lockout pin. Drive this pin high / low to enable / disable the device. If the enable function is not needed, tie this pin to VIN. Connect an external resistor divider network to set UVLO threshold.
10 NC P No connect pin. Leave floating or tie to GND.
11 ISNS+ I Current sense amplifier input. Connect the ISNS+ pin to the inductor side of the external current sense resistor using a low-current Kelvin connection.
12 VOUT I Output voltage sense and the current sense amplifier input. Connect the VOUT pin to the output side of the respective current sense resistor.
13 CONFIG I Configuration pin. Connect a resistor to ground to set primary/secondary, spread spectrum enable/disable, or interleaved operation.
14 RT I Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 200kHz and 2.2MHz.
15 EXTCOMP O External compensation pin. This pin is the output of the transconductance amplifier. If used, connect the compensation network from the EXTCOMP pin to AGND. Connect a 100kΩ resistor between the EXTCOMP and VDDA pins to use the internal compensation.
16 FB I Feedback pin. Connect a resistor between FB and VDDA to set the output voltage to 3.3V, 5V or 12V. Connect a resistor divider network from VOUT to FB to set the output voltage level between 0.8V to 36V. The voltage reference setpoint is 0.8V.
17 AGND G Analog ground pin. Ground return for the internal voltage reference and analog circuits.
18 VDDA P Internal analog bias regulator output pin. Connect a 0.1μF ceramic decoupling capacitor from VDDA to AGND as close as possible to the pins.
19 VCC P VCC bias supply pin. Connect a 4.7μF ceramic capacitors between VCC and PGND as close as possible to the pins.
20 SW1 P Switch pins. These pins form a switching node that is internally connected to the source terminal of the buck switch (high-side MOSFET) and the drain terminal of the synchronous rectifier (low-side MOSFET). Connect to the buck inductor.
21 SW2 P
22 SW3 P
23 PGND1 G Power ground pins. These pins form a power ground node for the low-side MOSFET. Connect to the system ground on a PCB. Path to CIN must be as short as possible.
24 PGND2 G
25 PGND3 G
26 PGND4 G
27 VIN1 P Converter input pins to the drain of the high-side power MOSFET. Connect to the input supply and the input filter capacitors. The path from the VIN pin to the input capacitors must be as short as possible.
28 VIN2 P
29 VIN3 P
30 PGND G Controller power ground pin. Connect to the system ground using multiple vias.
(1) P = Power, G = Ground, I = Input, O = Output.