SNVSCE8 July   2024 LM5190-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Wettable Flanks
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings 
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN)
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC, BIAS)
      3. 6.3.3  Precision Enable (EN)
      4. 6.3.4  Power-Good Monitor (PGOOD)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Low Dropout Mode
      7. 6.3.7  Dual Random Spread Spectrum (DRSS)
      8. 6.3.8  Soft Start
      9. 6.3.9  Output Voltage Setpoint (FB)
      10. 6.3.10 Minimum Controllable On Time
      11. 6.3.11 Inductor Current Sense (ISNS+, VOUT)
      12. 6.3.12 Voltage Loop Error Amplifier
      13. 6.3.13 Current Monitor, Programmable Current Limit, and Current Loop Error Amplifier (IMON/ILIM, ISET)
      14. 6.3.14 Dual Loop Architecture
      15. 6.3.15 PWM Comparator
      16. 6.3.16 Slope Compensation
      17. 6.3.17 High-Side and Low-Side Gate Drivers (HO, LO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode
      2. 6.4.2 Forced PWM Mode and Synchronization (FPWM/SYNC)
      3. 6.4.3 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 Power MOSFETs
        5. 7.1.1.5 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
    2. 7.2 Typical Applications
      1. 7.2.1 High Efficiency 400kHz CC-CV Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With Excel Quickstart Tool
          2. 7.2.1.2.2 Recommended Components
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Stage Layout
        2. 7.4.1.2 Gate-Drive Layout
        3. 7.4.1.3 PWM Controller Layout
        4. 7.4.1.4 Thermal Design and Layout
        5. 7.4.1.5 Ground Plane Design
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 PCB Layout Resources
        2. 8.2.1.2 Thermal Design Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

7.1.1.4 Power MOSFETs

The choice of power MOSFETs has significant impact on DC/DC regulator performance. A MOSFET with low on-state resistance, RDS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition times and reduced switching loss. Normally, the lower the RDS(on) of a MOSFET, the higher the gate charge and output charge (QG and QOSS, respectively), and vice versa. As a result, the product of RDS(on) and QG is commonly specified as a MOSFET figure-of-merit. Low thermal resistance of a given package makes sure that the MOSFET power dissipation does not result in excessive MOSFET die temperature.

The main parameters affecting power MOSFET selection are as follows:

  • RDS(on) at 7.5V.
  • Drain-source voltage rating, BVDSS.
  • Gate charge parameters at 7.5V.
  • Output charge, QOSS, at the relevant input voltage.
  • Body diode reverse recovery charge, QRR.
  • Gate threshold voltage, VGS(th), derived from the Miller plateau evident in the QG versus VGS plot in the MOSFET data sheet. To enhance MOSFET adequately, the miller plateau voltage must be 2V to 3V lower than the gate drive amplitude, especially at the minimum input voltage.

The MOSFET-related power losses for one channel are summarized by the equations presented in Table 7-1, where suffixes one and two represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic inductances and SW node ringing, are not included.

Table 7-1 MOSFET Power Losses
POWER LOSS MODE HIGH-SIDE MOSFET LOW-SIDE MOSFET
MOSFET conduction(2)(3)
Equation 20. P c o n d 1 = D × I L O A D 2 + ∆ I L O U T 2 12 × R D S ( o n ) 1
Equation 21. P c o n d 2 = D ' × I L O A D 2 + ∆ I L O U T 2 12 × R D S ( o n ) 2
MOSFET switching
Equation 22. P s w 1 = V S U P P L Y × f S W 2 × I L O A D - ∆ I L O U T 2 × t R + I L O A D + ∆ I L O U T 2 × t F
Negligible
MOSFET gate drive(1)
Equation 23. P g a t e 1 = V C C × f S W × Q G 1
Equation 24. P g a t e 2 = V C C × f S W × Q G 2
MOSFET output charge(4)
Equation 25. P C o s s = f S W × V S U P P L Y × Q O S S 2 + E o s s 1 - E o s s 2
Body diode
conduction		 N/A
Equation 26. P c o n d B D = V F × f S W × I L O A D + ∆ I L O U T 2 × t d t 1 + I L O A D - ∆ I L O U T 2 × t d t 2
Body diode
reverse recovery(5)
Equation 27. P R R = V S U P P L Y × f S W × Q R R 2
(1) Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally added series gate resistance and the relevant driver resistance of the device.
(2) MOSFET RDS(on) has a positive temperature coefficient of approximately 4500ppm/°C. The MOSFET junction temperature, TJ, and the rise over ambient temperature is dependent upon the device total power dissipation and the thermal impedance. When operating at or near minimum input voltage, make sure that the MOSFET RDS(on) is rated for the available gate drive voltage.
(3) D' = 1–D is the duty cycle complement.
(4) MOSFET output capacitances, Coss1 and Coss2, are highly non-linear with voltage. These capacitances are charged losslessly by the inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge the output capacitance of the low-side MOSFET. Eoss1, the energy of Coss1, is dissipated at turn-on, but this dissipation is offset by the stored energy Eoss2 on Coss2.
(5) MOSFET body diode reverse recovery charge, QRR, depends on many parameters, particularly forward current, current transition speed, and temperature.

The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically incurs most of the switching losses. Choosing a high-side MOSFET that balances conduction and switching loss contributions is imperative. The total power dissipation in the high-side MOSFET is the sum of the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the net loss attributed to body diode reverse recovery.

The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D interval). The low-side MOSFET switching loss is negligible as the low-side MOSFET switching loss is switched at zero voltage – current just communicates from the channel to the body diode or vice versa during the transition dead-times. The device, with the adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses scale directly with switching frequency.

In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching period. Therefore, to attain high efficiency, optimizing the low-side MOSFET for low RDS(on) is critical. In cases where the conduction loss is too high or the target RDS(on) is lower than available in a single MOSFET, connect two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode reverse recovery.