SNVSCE8 July   2024 LM5190-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Wettable Flanks
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings 
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN)
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC, BIAS)
      3. 6.3.3  Precision Enable (EN)
      4. 6.3.4  Power-Good Monitor (PGOOD)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Low Dropout Mode
      7. 6.3.7  Dual Random Spread Spectrum (DRSS)
      8. 6.3.8  Soft Start
      9. 6.3.9  Output Voltage Setpoint (FB)
      10. 6.3.10 Minimum Controllable On Time
      11. 6.3.11 Inductor Current Sense (ISNS+, VOUT)
      12. 6.3.12 Voltage Loop Error Amplifier
      13. 6.3.13 Current Monitor, Programmable Current Limit, and Current Loop Error Amplifier (IMON/ILIM, ISET)
      14. 6.3.14 Dual Loop Architecture
      15. 6.3.15 PWM Comparator
      16. 6.3.16 Slope Compensation
      17. 6.3.17 High-Side and Low-Side Gate Drivers (HO, LO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode
      2. 6.4.2 Forced PWM Mode and Synchronization (FPWM/SYNC)
      3. 6.4.3 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 Power MOSFETs
        5. 7.1.1.5 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
    2. 7.2 Typical Applications
      1. 7.2.1 High Efficiency 400kHz CC-CV Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With Excel Quickstart Tool
          2. 7.2.1.2.2 Recommended Components
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Stage Layout
        2. 7.4.1.2 Gate-Drive Layout
        3. 7.4.1.3 PWM Controller Layout
        4. 7.4.1.4 Thermal Design and Layout
        5. 7.4.1.5 Ground Plane Design
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 PCB Layout Resources
        2. 8.2.1.2 Thermal Design Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

5.5 Electrical Characteristics

TJ = –40°C to 125°C. Typical values are at TJ = 25°C, VIN = 12V, and EN tied to VIN (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY (VIN)
IQ-SD VIN shutdown current VEN = 0V 2.3 4.5 µA
IQ-SBY VIN standby current Non-switching, 0.5V ≤ VEN ≤ 1V 100 µA
ISLEEP1 Sleep current, 5V VIN = 24V, VVOUT = VBIAS = 5.0V, in sleep mode, VFPWM/SYNC = AGND, ISET floating 15 30 µA
ISLEEP2 Sleep current, 12V VIN = 24V, VVOUT = VBIAS = 12V, in sleep mode, VFPWM/SYNC = AGND, ISET floating 20 35 µA
ENABLE (EN)
VSBY-TH Shutdown to standby threshold VEN rising 0.55 V
VEN-TH Enable voltage rising threshold VEN rising, enable switching 0.95 1.0 1.05 V
VEN-HYS Enable hysteresis voltage 100 mV
INTERNAL LDO (VCC)
VVCC-REG VCC regulation voltage IVCC = 0mA to 110mA 7.125 7.5 7.875 V
VVCC-UVLO VCC UVLO rising threshold 4.65 4.8 4.95 V
VVCC-HYS VCC UVLO hysteresis 425 mV
IVCC-LIM Internal LDO short-circuit current limit 135 220 350 mA
EXTERNAL BIAS (BIAS)
VBIAS-TH VIN to VBIAS switchover rising threshold 8.55 9 9.45 V
VBIAS-HYS VIN to VBIAS switchover hysteresis 400 mV
REFERENCE VOLTAGE
VREF-V Regulated FB voltage VIMON = 0 V 792 800 808 mV
VREF-I Current loop reference voltage VFB = 0V 0.99 1 1.01 V
OUTPUT VOLTAGE (VOUT)
VOUT-5V 5V output voltage setpoint FB to AGND 4.95 5.0 5.05 V
VOUT-12V 12V output setpoint FB to VCC, VIN = 24V 11.88 12 12.12 V
ERROR AMPLIFIER (COMP)
gm-VEA Voltage loop EA transconductance ΔVFB = 100mV 1000 µS
gm-IEA Current loop EA transconductance ΔVIMON = 100mV 1000 µS
IFB Error amplifier input bias current 75 nA
ICOMP-SRC EA source current VCOMP = 1V 120 µA
ICOMP-SINK EA sink current VCOMP = 1V 120 µA
OUTPUT CURRENT MONITOR (IMON/ILIM)
gm-IMON Monitor amplifier gain from VCS VCS = 40mV 1.91 2 2.09 µA/mV
IOFFSET Monitor amplifier offset current VCS = 0mV 22.5 25 27.5 µA
CURRENT SETTING (ISET)
IISET ISET source current 9 10 11 µA
FORCED PWM MODE (FPWM/SYNC)
VZC-SW Zero-cross threshold SW-PGND threshold –5.5 mV
SWITCHING FREQUENCY
VRT RT pin regulation voltage 10kΩ < RRT < 220kΩ 1 V
FSW1 Switching frequency 1 VIN = 12V, RRT = 242kΩ to AGND 90 100 110 kHz
FSW2 Switching frequency 2 VIN = 12V, RRT = 10kΩ to AGND 2 2.2 2.4 MHz
VSLOPE Peak slope compensation amplitude Referenced to ISNS+ to VOUT input 45 mV
tON-MIN Minimum on-time 26 50 ns
tOFF-MIN Minimum off-time 80 125 ns
POWER GOOD (PGOOD)
VPG-UV Power-Good UV trip level Falling with respect to the regulated voltage 90% 92% 94%
VPG-OV Power-Good OV trip level Rising with respect to the regulated voltage 108% 110% 112%
VPG-UV-HYST Power-Good UV hysteresis 3.7%
VPG-OV-HYST Power-Good OV hysteresis 3.7%
VPG-OL PG voltage Open collector, IPG = 4mA 0.8 V
OVERVOLTAGE PROTECTION
VOVTH-RISING Overvoltage threshold Rising with respect to regulated voltage 108% 110% 112%
VOVTH-HYST Overvoltage threshold hysteresis 3.7%
STARTUP (Soft Start)
tSS-INT Internal fixed soft-start time 1.9 2.75 3.6 ms
BOOT CIRCUIT
VBOOT-DROP Internal diode forward drop ICBOOT = 20mA, VCC to CBOOT 0.8 1 V
IBOOT CBOOT to SW quiescent current, not switching VEN = 5V, VCBOOT-SW = 7.5V 25 µA
VBOOT-SW-UV-F CBOOT to SW UVLO falling threshold VCBOOT-SW falling 2.75 3.1 3.75 V
VBOOT-SW-UV-HYS CBOOT to SW UVLO hysteresis 0.3 V
HIGH-SIDE GATE DRIVER (HO)
VHO-HIGH HO high-state output voltage IHO = –100mA, VHO-HIGH = VCBOOT – VHO 300 mV
VHO-LOW HO low-state output voltage IHO = 100mA 75 mV
tHO-RISE HO rise time (10% to 90%) CLOAD = 2.7nF 20 ns
tHO-FALL HO fall time (90% to 10%) CLOAD = 2.7nF 8 ns
LOW-SIDE GATE DRIVER (LO)
VLO-HIGH LO high-state output voltage ILO = –100mA 300 mV
VLO-LOW LO low-state output voltage ILO = 100mA 75 mV
tLO-RISE LO rise time (10% to 90%) CLOAD = 2.7nF 20 ns
tLO-FALL LO fall time (90% to 10%) CLOAD = 2.7nF 8 ns
ADAPTIVE DEADTIME CONTROL
tDEAD1 HO off to LO on deadtime 21 ns
tDEAD2 LO off to HO on deadtime 21 ns
OVERCURRENT PROTECTION
VCS-TH Current limit threshold Measured from ISNS+ to VOUT 54 60 66 mV
VCS-TH-MIN Minimum peak current limit threshold Measured from ISNS+ to VOUT 12 mV
ACS CS amplifier gain 9.7 10 10.3 V/V
IBIAS-CS CS amplifier input bias current VVOUT = 5.0V 15 nA
VCS-NEG CS negative voltage threshold –30 mV
THERMAL SHUTDOWN
TJ-SD Thermal shutdown threshold (1) Temperature rising 175 °C
TJ-HYS Thermal shutdown hysteresis (1) 15 °C
(1) Specified by design. Not production tested.