SNVU581B November 2017 – June 2021 TPSM84424 , TPSM84624 , TPSM84824
Wire-loop test points and two scope probe test points have been provided as convenient connection points for digital voltmeters (DVM) or oscilloscope probes to aid in the evaluation of the device. A description of each test point follows:
| VIN S+ | Input voltage monitor. Connect the positive lead of a DVM to this point for measuring efficiency. |
| VIN S– | Input voltage monitor. Connect the negative lead of a DVM to this point for measuring efficiency. |
| VOUT S+ | Output voltage monitor. Connect the positive lead of a DVM to this point for measuring efficiency, line regulation, and load regulation. |
| VOUT S– | Output voltage monitor. Connect the negative lead of a DVM to this point for measuring efficiency, line regulation, and load regulation. |
| AGND | Analog ground test point. |
| PGND | Power ground test point. |
| VIN Scope (J3) | Input voltage scope monitor. Connect an oscilloscope to this set of points to measure input ripple voltage. |
| VOUT Scope (J4) | Output voltage scope monitor. Connect an oscilloscope to this set of points to measure output ripple voltage and transient response. |
| ENABLE | Enable test point. Connect this test point to AGND to disable the device. Leave this test point open to enable the device.The UVLO resistor divider (R24 and R25) is connected at this point. |
| PGOOD | Monitors the power good signal of the device. This is an open drain signal. |
| PULL_UP | Test point provided for applying a pull-up voltage for the PGOOD signal. A 100-kΩ pull-up resistor (R26) is present on the EVM between this test point and the PGOOD signal. |
| CLK | Synchronization clock input test point. An AC coupling capacitor (C13) is present on the EVM between this test point and the SYNC pin of the device. Pads for a termination resistor (R27) are present between this test point and PGND. An external clock signal can be applied to this point to synchronize the device to an appropriate frequency. |