SNVU663A June   2019  – May 2021 LP87524-Q1 , LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Setup
    1. 2.1 SCL/SDA Pins
    2. 2.2 NRST Pin
    3. 2.3 ENx (GPIOx) Pins
    4. 2.4 nINT
  4. 3Configuration
    1. 3.1 Default OTP Configurations
      1. 3.1.1 LP87524B-Q1 OTP Configuration
        1. 3.1.1.1 Startup and Shutdown Sequence
      2. 3.1.2 LP87524J-Q1 OTP Configuration
        1. 3.1.2.1 Startup and Shutdown Sequence
      3. 3.1.3 LP87524P-Q1 OTP Configuration
        1. 3.1.3.1 Startup and Shutdown Sequence
  5. 4References
  6. 5Revision History

3.1.2 LP87524J-Q1 OTP Configuration

Table 3-8 BUCK0, BUCK1, BUCK2, BUCK3 OTP Settings
DescriptionBit NameLP87524J-Q1Configurable
General settingsBuck phase configuration (e.g. four single phase denoted as 1+1+1+1, four phase single output denoted as 4 ph).N/A1+1+1+1No
Switching frequencyN/A4 MHzNo
Spread spectrumEN_SPREAD_SPECNoYes
Startup and shutdown delay range, 0...4.8 ms / 0... 9.6 ms / 0...15 ms / 0...30 msDOUBLE_DELAY, HALF_DELAY0...15 msYes
BUCK0Output voltageBUCK0_VSET3300 mVYes
Enable, ENx-pin or I2C registerEN_BUCK0, EN_PIN_CTRL0, BUCK0_EN_PIN_SELECTI2C and EN1Yes
Force PWM mode or auto modeBUCK0_FPWMautoYes
Force multiphase mode or auto modeBUCK0_FPWM_MPautoYes
Peak current limitILIM02.5 AYes
Slew rateSLEW_RATE03.8 mV/µsYes
Startup DelayBUCK0_STARTUP_DELAY5 msYes
Shutdown DelayBUCK0_SHUTDOWN_DELAY0 msYes
BUCK1Output voltageBUCK1_VSET1200 mVYes
Enable, EN-pin or I2C registerEN_BUCK1, EN_PIN_CTRL1, BUCK1_EN_PIN_SELECTI2C and EN1Yes
Force PWM mode or auto modeBUCK1_FPWMautoYes
Peak current limitILIM12.5 AYes
Slew rateSLEW_RATE13.8 mV/µsYes
Startup DelayBUCK1_STARTUP_DELAY5 msYes
Shutdown DelayBUCK1_SHUTDOWN_DELAY0 msYes
BUCK2Output voltageBUCK2_VSET1000 mVYes
Enable, ENx-pin or I2C registerEN_BUCK2, EN_PIN_CTRL2, BUCK2_EN_PIN_SELECTI2C and EN1Yes
Force PWM mode or auto modeBUCK2_FPWMForce PWMYes
Force multiphase mode or auto modeBUCK2_FPWM_MPautoYes
Peak current limitILIM25 AYes
Slew rateSLEW_RATE23.8 mV/µsYes
Startup DelayBUCK2_STARTUP_DELAY2 msYes
Shutdown DelayBUCK2_SHUTDOWN_DELAY0 msYes
BUCK3Output voltageBUCK3_VSET1800 mVYes
Enable, EN-pin or I2C registerEN_BUCK3, EN_PIN_CTRL3, BUCK3_EN_PIN_SELECTI2C and EN1Yes
Force PWM mode or auto modeBUCK3_FPWMForce PWMYes
Peak current limitILIM33.5 AYes
Slew rateSLEW_RATE33.8 mV/µsYes
Startup DelayBUCK3_STARTUP_DELAY0 msYes
Shutdown DelayBUCK3_SHUTDOWN_DELAY1 msYes

Table 3-9 lists the device settings for GPIOs.

Table 3-9 EN, CLKIN and GPIO Pin Settings
DescriptionBit NameLP87524J-Q1Configurable
EN1 (GPIO1) pinEN1 (GPIO1) pin pulldown resistor enable or disableEN1_PDEnabledYes
EN2 (GPIO2) pinEN2 (GPIO2) pin pulldown resistor enable or disableEN2_PDDisabledYes
EN3 (GPIO3) pinEN3 (GPIO3) pin pulldown resistor enable or disableEN3_PDDisabledYes
CLKIN pinCLKIN pin pull-down resistor enable or disableCLKIN_PDEnabledYes
Frequency of external clock when connected to CLKINEXT_CLK_FREQ2 MHzYes
Mode for the internal PLL. When PLL disabled, internal RC OSC is usedPLL_MODE[1:0]EnabledYes
EN1 (GPIO) controlEnable or GPIOGPIO1_SELEnableYes
Input or output in GPIO modeGPIO1_DIRInputYes
Output type open drain or push-pullGPIO1_ODPush-pullYes
EN2 (GPIO) controlEnable or GPIOGPIO2_SELGPIOYes
Input or output in GPIO modeGPIO2_DIROutputYes
Output type open drain or push-pullGPIO2_ODOpen drainYes
Pin control of GPIO, EN1 or EN3EN_PIN_CTRL_GPIO2, EN_PIN_SELECT_GPIO2EN1Yes
Startup DelayGPIO2_STARTUP_DELAY5 msYes
Shutdown DelayGPIO2_SHUTDOWN_DELAY0 msYes
EN3 (GPIO) controlEnable or GPIOGPIO3_SELGPIOYes
Input or output in GPIO modeGPIO3_DIROutputYes
Output type open drain or push-pullGPIO3_ODOpen drainYes
Pin control of GPIO, EN1 or EN2EN_PIN_CTRL_GPIO3, EN_PIN_SELECT_GPIO3EN1Yes
Startup DelayGPIO3_ STARTUP_ DELAY3 msYes
Shutdown DelayGPIO3_ SHUTDOWN_ DELAY0 msYes

Table 3-10 shows device settings for PGOOD.

Table 3-10 PGOOD OTP Settings
DescriptionBit NameLP87524J-Q1Configurable
Signals monitored by PGOODBUCKx output voltage / voltage and current (master bucks)PGx_SELVoltageYes
PGOOD mode selectionsPGOOD thresholds for BUCKx (Undervoltage / Window (undervoltage and overvoltage))PGOOD_WINDOWWindowYes
PGOOD valid debounce timePGOOD_SET_DELAY11 msYes
PGOOD signal mode (status / latched until fault source read)EN_PGFLT_STATStatusYes
PGOOD output mode (push-pull or open drain)PGOOD_ODOpen drainYes
PGOOD polarity (active high / active low)PGOOD_POLActive high (power valid)Yes

Table 3-11 lists the device settings for thermal warning. Also refer to Table 3-13 for interrupt settings.

Table 3-11 Protections OTP Settings
DescriptionBit NameLP87524J-Q1Configurable
ProtectionsThermal warning level (125°C or 137°C)TDIE_WARN_LEVEL137°CYes
Input over-voltage protectionN/AEnabledNo

Table 3-12 shows device settings for I2C and OTP revision ID values.

Table 3-12 Device Identification and I2C Settings
DescriptionBit NameLP87524J-Q1Configurable
I2C slave ID (7-bit)Slave addressN/A0x60No

Table 3-13 lists device settings for interrupts. When interrupt from an event is unmasked, an interrupt is generated to nINT pin.

Table 3-13 Interrupt Mask Settings
Interrupt eventBit NameLP87524J-Q1Configurable
GeneralSync clock appears or disappearsSYNC_CLK_MASKUnmaskedYes
Thermal warningTDIE_WARN_MASKUnmaskedYes
Load measurement readyI_LOAD_READY_MASKMaskedYes
Register resetRESET_REG_MASKMaskedYes
BUCK0Buck0 PGOOD has reached threshold levelBUCK0_PG_MASKMaskedYes
Buck0 current limit triggeredBUCK0_ILIM_MASKMaskedYes
BUCK1Buck1 PGOOD has reached threshold levelBUCK1_PG_MASKMaskedYes
Buck1 current limit triggeredBUCK1_ILIM_MASKMaskedYes
BUCK2Buck2 PGOOD has reached threshold levelBUCK2_PG_MASKMaskedYes
Buck2 current limit triggeredBUCK2_ILIM_MASKMaskedYes
BUCK3Buck3 PGOOD has reached threshold levelBUCK3_PG_MASKMaskedYes
Buck3 current limit triggeredBUCK3_ILIM_MASKMaskedYes