SNVU663A June   2019  – May 2021 LP87524-Q1 , LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Setup
    1. 2.1 SCL/SDA Pins
    2. 2.2 NRST Pin
    3. 2.3 ENx (GPIOx) Pins
    4. 2.4 nINT
  4. 3Configuration
    1. 3.1 Default OTP Configurations
      1. 3.1.1 LP87524B-Q1 OTP Configuration
        1. 3.1.1.1 Startup and Shutdown Sequence
      2. 3.1.2 LP87524J-Q1 OTP Configuration
        1. 3.1.2.1 Startup and Shutdown Sequence
      3. 3.1.3 LP87524P-Q1 OTP Configuration
        1. 3.1.3.1 Startup and Shutdown Sequence
  5. 4References
  6. 5Revision History

2.3 ENx (GPIOx) Pins

Enable pins EN1 (GPIO1), EN2 (GPIO2), EN3 (GPIO3) (pins 7, 15, 2) are I2C configurable GPIO pins. The direction, function, and output type (open-drain or push-pull) are programmable for the GPIOs. When configured as EN pin, they can be used to start the buck converter startup sequence based on programmed timing. Shutdown times can be programmed as well. Drive these pins low to disable and high to enable when programmed as enable signal.