SNVU737A December   2020  – December 2021 LM5123-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Applications
    2. 1.2 Features
  3. 2EVM Setup
    1. 2.1 EVM Characteristics
    2. 2.2 EVM Connectors and Test Points
    3. 2.3 EVM Configurations
      1. 2.3.1 Output Voltage Tracking
  4. 3Test Setup and Procedures
    1. 3.1 Equipment
  5. 4Test Results
    1. 4.1 Efficiency
    2. 4.2 Load Regulation
    3. 4.3 Thermal Performance
    4. 4.4 Start-up Waveforms
    5. 4.5 Steady State Operation
    6. 4.6 Load Transient Response
    7. 4.7 Output Voltage Tracking
  6. 5PCB Layers
  7. 6Schematic
  8. 7Bill of Materials
  9. 8Revision History

2.2 EVM Connectors and Test Points

Section 2.2 describes the connection points of the evaluation module. Table 2-2 to Table 2-4 describe these connections. Table 2-2 lists the power connections of the evaluation module. These connections are intended to handle relatively large currents.

Table 2-2 Power Connections
Jumper Pin Description
J1 VIN+ Positive input voltage power for the evaluation module
J2 VOUT+ Positive output voltage power for the evaluation module
J4 GND Negative output voltage power for the evaluation module
J5 VIN- Negative input voltage power for the evaluation module

Table 2-3 lists the EVM jumpers and test points that configure the LM5123-Q1 as desired. These jumpers can set different modes of operation or provide signals to different pins of the LM5123-Q1.

Table 2-3 Programmable Jumper Connections
Jumper Pins Description Default Connection
J7 Pin 1 to Pin 2 SYNC/DITHER/VH/CP is pulled to VCC through a 1-kΩ resistor to enable the internal charge pump or enable the VCC hold up functionality. This connection should not be made if the J10 is populated
Pin 2 to Pin 3 SYNC/DITHER/VH/CP is pulled to AGND through a 1-kΩ resistor to disable the internal charge-pump and VCC hold up functionality
Open If using an external clock synchronization on J10, leave this jumper open. X
J9 VTRK_D PWM signal applied through a two stage low pass filter to the TRK pin. R18 must be populated.
J10 Pin 1 to Pin 2 SYNC/DITHER/VH/CP pulled to ground disabling dithering, internal charge-pump functionality and VCC hold up functionality. Should not be populated when J7 is populated between pin 1 and pin 2 X
Open Dithering is enabled. To synchronize to an external clock C33 should be removed.
J11 Pin 1 to Pin 2 Bypass D1 to tie either the VIN or VOUT nets to the BIAS pin X
Open Either VIN or VOUT is supplied through D1 to the BIAS pin
J12 Pin 1 to Pin 2 VIN is supplied to the BIAS pin. This is the default connection X
Pin 2 to Pin 3 VOUT is supplied to the BIAS pin
J13 Pin 1 to Pin 2 Connect an auxiliary power supply can be used to supply power to the BIAS pin. J11 should be open if this is populated
Pin 2 to Pin 3 Connect the VCC and VIN pin
Open X
J14 Pin 1 to Pin 2 Configures light load switching operation to be FPWM X
Pin 2 to Pin 3 Configures light load switching operation to be diode emulation
Open Configures light load switching operation to be skip
TP6 Positive input to the VAUX net
TP7 Negative input to the VAUX net
TP8 Positive input to the TRK pin of the LM5123-Q1
TP9 Negative input to the TRK pin of the LM5123-Q1

Table 2-4 indicates the dedicated voltage probe points of the EVM. These points are used to make measurements on the EVM.

Table 2-4 Probe Points
Sense Point Name Description
TP1 VIN+ Sense point for the positive input voltage
TP2 VOUT+ Sense point for the positive output voltage
TP3 SW Sense point for the switch node of the boost controller
TP4 GND Sense point for the negative output voltage
TP5 VIN- Sense point for the negative input voltage
J3 PGND Power ground connection
J6 PGND Power ground connection
J8 Probe point for many of the LM5123 control signals
1 BIAS
2 PGOOD
3 UVLO
4 COMP
5 SS
6 AGND