The Main tab (see for example Figure 3-9) has the elemental controls for the EVM and provides a view to the chip status. Starting from top, the main controls are:

• I2C mode or 4 Enable mode. If this states I2C mode, device is controlled with I2C. When this states 4EN mode, bucks are controlled with ENx pins.
• Assert NRST: This checkbox will assert high level to LP875761-Q1 NRST pin. This pin enables the chip internal voltage reference and bias circuitry.
• Assert EN1: This checkbox will assert high level to LP875761-Q1 EN1 pin. Asserting EN1 may enable the buck regulator(s) or switch to different output voltage level, depending on the register settings.
• Assert EN2: This checkbox will assert high level to LP875761-Q1 EN2 pin. Asserting EN2 may enable the buck regulator(s) or switch to different output voltage level, depending on the register settings.
• Assert EN3: This checkbox will assert high level to LP875761-Q1 EN3 pin. Asserting EN3 may enable the buck regulator(s) or switch to different output voltage level, depending on the register settings.
• Assert EN4: In 4 Enable mode, this checkbox will assert high level to LP875761-Q1 SCL pin, (alternative function is EN4). Asserting EN4 may enable one or more of the buck regulators, depending on the register settings. This checkbox is visible only when device is configured to 4 Enable Signal Mode.
• Assert SW Reset: To perform a complete SW reset to the chip, assert this checkbox. See the LP875761-Q1 datasheet for explanation of LP875761-Q1 reset scenarios.

The Bucks section provides status information and enable controls for all the 4 buck cores. On the left of the section are the check-boxes for the buck enable bits. The Mode field provides information on each of the buck core and can have any of the values given in Table 4-1:

The Multiphase status info field tells whether a buck core is configured as a master or a slave. The "Current" field gives the result of the buck converter load current measurement operation. Output currents of each buck core and total output current of one or more of the masters are shown on the fields.

The System Flags / Interrupts section as well as the Interrupt bits and the Status bits sections give data on system faults and warnings. If the interrupt is set for any reason the Interrupt active field shall show ‘1’ on red background. The flag causing the interrupt will also be set on the Main tab. Interrupts on LP875761-Q1 can only be cleared by writing '1’ to associated registers. Any individual flag can be cleared by clicking the Clear button next to each flag field. Some of the flags also have a mask bits. If Mask check-box of certain flag is checked, the interrupt is not generated. The Status bits will show the current status of the faults.

The Power Good section is for Power Good pin control and indication. It includes the latched values of buck Power Good Faults. These can be cleared with the Clear -button.

At the bottom of the GUI window is the Auto Write checkbox. If Auto Write is checked (default) any checking, un-checking or pulldown menu selections will immediately launch I²C writes to the chip register(s). If not checked, the user can update the chip registers to correspond the configuration selected on the GUI by clicking Write Registers.

If Poll Status is selected the software sends a query to the LP875761-Q1 at a fixed interval in order to detect the status of the chip, including operation mode, multi-phase status, and output current. If also the Poll Only Pins is selected the software is monitoring only the state of Interrupt and Powergood pins. If Poll Status is not selected or if Poll Only Pins is selected, user can read the registers by applying Read Registers. Bus Speed pulldown menu selections are given in Table 4-2 below and is instantly applied for System I²C.