6 Board Layout

This section describes the board layout of the LP875761Q1EVM. See the LP875761-Q1 data sheet for specific PCB layout recommendations.

The board is constructed on a 4-layer PCB. using 55-µm copper on top and bottom layers to reduce resistance and improve heat transfer.

Board stack-up is shown in Figure 6-1. Figure 6-2 shows the top view of the entire board and Figure 6-3 through Figure 6-8 show the component placement, layout, and 3D view close to the LP875761-Q1 device.

Figure 6-1 Board Stack-Up

The design utilizes dual side placement of the components. This allows placement of the inductors next to the LP875761-Q1 device for reducing SW node area for improved efficiency and reduced EMI. SW nets have also snubber components to reduce SW pin spiking and EMI. The input capacitors can be placed very close to the LP875761-Q1 device, to bottom side, to keep parasitic inductances low, and there is also space for input filters for further EMI reduction.

Figure 6-2 Top View of the LP875761-Q1EVM

Figure 6-3 Component Placement Top Layer

Figure 6-4 Component Placement Bottom Layer

VIN nets are connected to bottom layer with multiple vias. This allows closer placement of the inductors, thus reducing SW node size and EMI. Also snubber circuits are placed next to SW nets for EMI reduction. Multiple GND vias are used to provide solid ground around the LP875761-Q1 device.

Figure 6-5 Top Layer

GND plane close to top layer (0.143 mm) helps to reduce parasitic inductance. Holes in the plane are under inductor footprint (SW node) to reduce parasitic capacitance of the SW node, thus reducing noise coupling and improving efficiency.

Figure 6-6 Mid-Layer1

VIN supply is routed in this layer between the ground planes to reduce radiated emissions. VIN and GND vias are placed in hatched pattern to avoid large gaps in these planes.

Figure 6-7 Mid-Layer2

Input capacitors and filters are placed under the LP875761-Q1 into bottom layer. This allows closer placement of the inductors and input components reducing SW and VIN net areas and improving EMI.

Figure 6-8 Bottom Layer (note mirror view)