SNVU753A November   2019  – May 2021 TPS542A52

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Before You Begin
  3. 2Description
    1. 2.1 Typical End-User Applications
    2. 2.2 EVM Features
    3. 2.3 TPS542A52EVM-059 PCB
  4. 3TPS542A52EVM-059 Bottom Circuit
    1. 3.1 Modifications
      1. 3.1.1 Output Voltage Setpoint
      2. 3.1.2 Enable and Undervoltage Lockout
      3. 3.1.3 External Clock Synchronization
      4. 3.1.4 Load Step with Function Generator
    2. 3.2 Bottom Circuit Schematic
    3. 3.3 Test Setup and Results
      1. 3.3.1  Input/Output Connections
      2. 3.3.2  Start Up Procedure
      3. 3.3.3  Electrical Performance Specifications and Results
      4. 3.3.4  Efficiency
      5. 3.3.5  Power Loss
      6. 3.3.6  Load Regulation
      7. 3.3.7  Transient Response
      8. 3.3.8  Loop Response
      9. 3.3.9  Output Voltage Ripple
      10. 3.3.10 Thermal Data
  5. 4TPS542A52EVM-059 Top Circuit (Small Layout Area Design)
    1. 4.1 Modifications
      1. 4.1.1 Output Voltage Setpoint
      2. 4.1.2 Enable and Undervoltage Lockout
      3. 4.1.3 External Clock Synchronization
      4. 4.1.4 Load Step with Function Generator
    2. 4.2 TPS542A52EVM-059 Top Circuit (Small Layout Area) Schematic
    3. 4.3 Test Setup and Results
      1. 4.3.1  Input/Output Connections
      2. 4.3.2  Start Up Procedure
      3. 4.3.3  Electrical Performance Specifications and Results
      4. 4.3.4  Efficiency
      5. 4.3.5  Power Loss
      6. 4.3.6  Load Regulation
      7. 4.3.7  Line Regulation
      8. 4.3.8  Transient Response
      9. 4.3.9  Loop Response
      10. 4.3.10 Output Voltage Ripple
      11. 4.3.11 Start Up
  6. 5TPS542A52EVM-059 PCB Layout
  7. 6List of Materials
  8. 7Revision History

4.1.1 Output Voltage Setpoint

The output voltage is set by the resistor divider network of R5_2 and R10_2, as shown in Figure 4-1. The divider is connected between SREF and AGND pins, where the mid-point of the divider is tapped to the VSET pin. Unlike many converters, the output voltage is not set by connecting a resistor divider directly to the output node. This allows the use of a differential remote sense for improved output voltage accuracy.

It is recommended to use R5_2 and R10_2 in the range of 1 kΩ to 100 kΩ, and the total impedance must be greater than 10 kΩ. A footprint for a small capacitor, C22_2, has been added for high frequency noise filtering, but is typically not necessary and is not populated by default.

The value of R5_2 for a desired output voltage, VOUT, can be calculated using Equation 2.

Equation 2. GUID-8A4C0FC6-1616-4A19-A233-BA442A6DD94F-low.gif

where

  • VSREF = 1.2 V
  • R10_2 = 20.0 kΩ

Note that for Vout below 1 V, the value of R10_2 should be reduced to keep R5_2 and R10_2 between 1 kΩ and 100 kΩ, while still maintaining a total impedance greater than 10 kΩ.