SNVU753A November   2019  – May 2021 TPS542A52

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Before You Begin
  3. 2Description
    1. 2.1 Typical End-User Applications
    2. 2.2 EVM Features
    3. 2.3 TPS542A52EVM-059 PCB
  4. 3TPS542A52EVM-059 Bottom Circuit
    1. 3.1 Modifications
      1. 3.1.1 Output Voltage Setpoint
      2. 3.1.2 Enable and Undervoltage Lockout
      3. 3.1.3 External Clock Synchronization
      4. 3.1.4 Load Step with Function Generator
    2. 3.2 Bottom Circuit Schematic
    3. 3.3 Test Setup and Results
      1. 3.3.1  Input/Output Connections
      2. 3.3.2  Start Up Procedure
      3. 3.3.3  Electrical Performance Specifications and Results
      4. 3.3.4  Efficiency
      5. 3.3.5  Power Loss
      6. 3.3.6  Load Regulation
      7. 3.3.7  Transient Response
      8. 3.3.8  Loop Response
      9. 3.3.9  Output Voltage Ripple
      10. 3.3.10 Thermal Data
  5. 4TPS542A52EVM-059 Top Circuit (Small Layout Area Design)
    1. 4.1 Modifications
      1. 4.1.1 Output Voltage Setpoint
      2. 4.1.2 Enable and Undervoltage Lockout
      3. 4.1.3 External Clock Synchronization
      4. 4.1.4 Load Step with Function Generator
    2. 4.2 TPS542A52EVM-059 Top Circuit (Small Layout Area) Schematic
    3. 4.3 Test Setup and Results
      1. 4.3.1  Input/Output Connections
      2. 4.3.2  Start Up Procedure
      3. 4.3.3  Electrical Performance Specifications and Results
      4. 4.3.4  Efficiency
      5. 4.3.5  Power Loss
      6. 4.3.6  Load Regulation
      7. 4.3.7  Line Regulation
      8. 4.3.8  Transient Response
      9. 4.3.9  Loop Response
      10. 4.3.10 Output Voltage Ripple
      11. 4.3.11 Start Up
  6. 5TPS542A52EVM-059 PCB Layout
  7. 6List of Materials
  8. 7Revision History

3.3.1 Input/Output Connections

The TPS542A52EVM-059 is provided with input/output connectors and test points as shown in Table 3-2. A power supply capable of supplying at least 5 A at the desired EVM input voltage must be connected to J1 through a pair of 20-AWG or greater wires. The load must be connected to J2 through a pair of 18-AWG or greater wires. The maximum load current capability is 15 A.

Wire lengths must be minimized to reduce losses and parasitic inductance in the wires. PVIN+ (TP1) provides a test point to monitor the VIN input voltages with PVIN- (TP2) providing a convenient reference to PGND. VOUT+ (TP6) is used to monitor the output voltage with VOUT- (TP7) providing a reference to PGND.

Table 3-2 Top Circuit Connections and Test Points
CONNECTION AND TEST POINTSDESCRIPTION
J1VIN, PGND connection (see Table 1-1 for input voltage range)
J2VOUT, PGND connection: 5.5 V at 15 A maximum (default is 1 V out at 15 A)
J3Programming mode and external clock synchronization
J4Enable configuration
J5Output current sensing points when using function generator as load control signal
J6Not utilized in this EVM
PVIN+ (TP1), PVIN- (TP2)VIN voltage sensing test points
VOUT+ (TP6), VOUT- (TP7)VOUT voltage sensing test points
AVIN (TP3)AVIN voltage sensing test points
VREG (TP4)VREG voltage sensing test point
SW+ (TP5), SW- (TP18)SW node sensing test points
CHA (TP9), CHB (TP8)Loop measurement test points
EN (TP10)EN pin test point
PGD (TP11)Open-drain PGD test point
SYNC_CLK (TP12)For connecting and measuring external clock synchronization
AGND (TP13, TP14, TP15)AGND connection - multiple provided to reduce oscilloscope ground probe loop inductance
PGND (TP17)PGND connection
FGEN+ (TP19), FGEN- (TP20)Function generator connection points - referenced to PGND